DS12C887A Datasheet, PDF (2/2 Pages) Dallas Semiconductor – Real-Time Clock

DS12C887A
to clear the RAM, RCLR must be forced to an input logic 0 (-0.3V to +0.8V) during battery-backup mode
when V_CC is not applied. The RCLR function is designed to be used via human interface (shorting to
ground manually or by switch) and not to be driven with external buffers.
For a complete description of operating conditions, electrical characteristics, bus timing and pin
descriptions other than RCLR , see the DS12C887 data sheet.
DS12C887 REAL-TIME CLOCK PLUS RAM
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
24-PIN
MIN
MAX
1.320 1.335
33.53 33.91
0.675 0.700
17.15 17.78
0.345 0.370
8.76 9.40
0.100 0.130
2.54 3.30
0.015 0.030
0.38 0.76
0.110 0.140
2.79 3.56
0.090 0.110
2.29 2.79
0.590 0.630
14.99 16.00
0.008 0.012
0.20 0.30
0.015 0.021
0.38 0.53
.
Note: Pins 2, 3, 16, 20, and 22 are missing by design.
This device cannot be stored or shipped in conductive
material that will give a continuity path between the RAM
clear pin and ground.
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