DS1245W Datasheet, PDF (2/11 Pages) Dallas Semiconductor – 3.3V 1024k Nonvolatile SRAM

DS1245W
DESCRIPTION
The DS1245W 3.3V 1024k Nonvolatile SRAM is a 1,048,576-bit, fully static, nonvolatile SRAM
organized as 131,072 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V_CC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1245W devices can be used in place of existing 128k
x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs
(A₀ - A₁₆) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t_ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting
parameter is either t_CO for CE or t_OE for OE rather than address access.
WRITE MODE
The DS1245W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t_WR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in t_ODW from its falling edge.
DATA RETENTION MODE
The DS1245W provides full functional capability for V_CC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V_CC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V_CC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V_CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V_CC rises above approximately 2.5 volts, the power
switching circuit connects external V_CC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V_CC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1245W device is shipped from Dallas Semiconductor with its lithium energy source
disconnected, guaranteeing full energy capacity. When V_CC is first applied at a level greater than 3.0
volts, the lithium energy source is enabled for battery back-up operation.
PACKAGES
The DS1245W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
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