DS1230W Datasheet, PDF (2/11 Pages) Dallas Semiconductor – 3.3V 256k Nonvolatile SRAM

DS1230W
DESCRIPTION
The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors V_CC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230W devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W
devices in the PowerCap Module package are directly surface mountable and are normally paired with a
DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of
write cycles that can be executed and no additional support circuitry is required for microprocessor
interfacing.
READ MODE
The DS1230W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A₀ – A₁₄) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t_ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either t_CO for CE or t_OE for OE rather than address access.
WRITE MODE
The DS1230W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t_WR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in t_ODW from its falling edge.
DATA RETENTION MODE
The DS1230W provides full functional capability for V_CC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V_CC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V_CC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V_CC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V_CC rises above approximately 2.5 volts, the power
switching circuit connects external V_CC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V_CC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1230W device is shipped from Dallas Semiconductor with its lithium energy source
disconnected, guaranteeing full energy capacity. When V_CC is first applied at a level greater than 3.0
volts, the lithium energy source is enabled for battery back-up operation.
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