DS1210_03 Datasheet, PDF (2/6 Pages) Dallas Semiconductor – Nonvolatile Controller Chip

DS1210
OPERATION
The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM.
First, a switch is provided to direct power from the battery or the incoming supply (V_CCI) depending on
which is greater. This switch has a voltage drop of less than 0.3V. The second function which the
nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming
supply. When the supply goes out of tolerance a precision comparator detects power-fail and inhibits chip
enable ( CEO ). The third function of write protection is accomplished by holding the CEO output signal to
within 0.2 volts of the V_CCI or battery supply. If CE input is low at the time power-fail detection occurs,
the CEO output is kept in its present state until CE is returned high. The delay of write protection until
the current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the
range of 4.75 volts to 4.5 volts with the tolerance Pin 3 grounded. If Pin 3 in connected to V_CCO, then
power-fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions
CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210
performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is
powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than
2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by
performing a read cycle after power-up to any location in memory, verifying that memory location
content. A subsequent write cycle can then be executed to the same memory location altering the data. If
the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in
danger of being corrupted. The fifth function of the nonvolatile controller provides for battery
redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to
use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which
allows the connection of two batteries. During battery backup operation the battery with the highest
voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a
redundant battery is transparent to circuit operation and to the user. A battery status warning will occur
when the battery in use falls below 2.0 volts. A grounded V_BAT2 pin will not activate a battery-fail
warning. In applications where battery redundancy is not required, a single battery should be connected to
the BAT1 pin. The BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to
turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is
powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and V_CCO
will be forced to V_OL. When the batteries are first attached to one or both of the V_BAT pins, V_CCO will not
provide battery back-up until V_CCI exceeds V_CCTP, as set by the T_OL pin, and then falls below V_BAT.
Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section
A shows the connections necessary to write protect the RAM when V_CC is less than 4.75 volts and to back
up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when V_CC is
less than 4.75 volts and to delay its restart on power-up to prevent spurious writes.
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