DS5001FP Datasheet, PDF (19/26 Pages) Dallas Semiconductor – 128k Soft Microprocessor Chip

DS5001FP
AC CHARACTERISTICS (continued)
BYTE-WIDE ADDRESS/DATA BUS TIMING
(T_A = 0°C to +70°C; V_CC = 5V ±10%)
#
PARAMETER
SYMBOL MIN MAX UNITS
Delay to Byte-Wide Address Valid from
40 CE1 , CE2 , or CE1N Low During Op Code
t_CE1LPA
30
ns
Fetch
41 Pulse Width of CE 1-4, PE 1-4 or CE1N
t_CEPW
4t_CLK - 35
ns
42 ^{Byte-Wide Address Hold After CE1 , CE2 , or}
t_CE1HPA
2t_CLK - 20
ns
CE1N High During Op Code Fetch
43 ^{Byte-Wide Data Setup to CE1 , CE2 , or CE1N}
High During Op Code Fetch
t_OVCE1H
1t_CLK + 40
ns
44 ^{Byte-Wide Data Hold After CE1 , CE2 or}
CE1N High During Op Code Fetch
t_CE1HOV
0
ns
45 ^{Byte-Wide Address Hold After CE 1-4,}
PE 1-4, or CE1N High During MOVX
t_CEHDA
4t_CLK - 30
ns
Delay from Byte-Wide Address Valid
46
CE 1-4, PE 1-4, or CE1N Low During MOVX
t_CELDA
4t_CLK - 35
ns
47 ^{Byte-Wide Data Setup to CE 1-4, PE 1-4, or}
CE1N High During MOVX (read)
t_DACEH
1t_CLK + 40
ns
48 ^{Byte-Wide Data Hold After CE 1-4,}
PE 1-4, or CE1N High During MOVX (read)
t_CEHDV
0
ns
49 ^{Byte-Wide Address Valid to R/ W Active}
During MOVX (write)
t_AVRWL
3t_CLK - 35
ns
50 ^{Delay from R/ W Low to Valid Data Out}
During MOVX (write)
t_RWLDV
20
ns
51 ^{Valid Data-Out Hold Time from CE 1-4,}
PE 1-4, or CE1N High
t_CEHDV
1t_CLK - 15
ns
52 Valid Data-Out Hold Time from R/ W High
t_RWHDV
0
ns
53 _{Write Pulse Width (R/ W Low Time)}
t_RWLPW
6t_CLK - 20
ns
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