DS5001FP Datasheet, PDF (13/26 Pages) Dallas Semiconductor – 128k Soft Microprocessor Chip

AC CHARACTERISTICS
DS5001FP
EXPANDED BUS MODE TIMING SPECIFICATIONS
(T_A = 0°C to +70°C; V_CC = 5V ±10%)
#
PARAMETER
SYMBOL MIN
MAX UNITS
1 Oscillator Frequency
1/ t_CLK
1.0
16
MHz
2 ALE Pulse Width
t_ALPW
2t_CLK - 40
ns
3 Address Valid to ALE Low
t_AVALL
t_CLK - 40
ns
4 Address Hold After ALE Low
t_AVAAV
t_CLK - 35
ns
ALE Low to Valid Instruction In
5
at 12MHz
at 16MHz
t_ALLVI
4t_CLK - 150
4t_CLK - 90
ns
ns
6 ALE Low to PSEN Low
t_ALLPSL
t_CLK - 25
ns
7 _{PSEN Pulse Width}
t_PSPW
3t_CLK - 35
ns
PSEN Low to Valid Instruction In
8
at 12MHz
at 16MHz
9 ^{Input Instruction Hold After PSEN Going}
High
t_PSLVI
t_PSIV
ns
3t_CLK - 150
ns
3t_CLK - 90
0
ns
10 ^{Input Instruction Float After PSEN Going}
High
t_PSIX
t_CLK - 20
ns
11 Address Hold After PSEN Going High
Address Valid to Valid Instruction In
12
at 12MHz
at 16MHz
13 PSEN Low to Address Float
14 RD Pulse Width
t_PSAV
t_CLK - 8
ns
t_AVVI
5t_CLK - 150
5t_CLK - 90
ns
ns
t_PSLAZ
0
ns
t_RDPW
6t_CLK - 100
ns
15 _{WR Pulse Width}
t_WRPW
6t_CLK - 100
ns
16 ^{RD Low to Valid Data In}
17 Data Hold After RD High
at 12MHz
at 16MHz
t_RDLDV
t_RDHDV
5t_CLK - 165
ns
5t_CLK - 105
ns
0
ns
18 Data Float After RD High
t_RDHDZ
2t_CLK - 70
ns
19 ^{ALE Low to Valid Data In}
at 12MHz
at 16MHz
t_ALLVD
8t_CLK - 150
8t_CLK - 90
ns
20
Valid Address to Valid Data In
at 12MHz
at 16MHz
t_AVDV
9t_CLK - 165
9t_CLK - 105
ns
21 ALE Low to RD or WR Low
t_ALLRDL
3t_CLK - 50 3t_CLK + 50
ns
22 Address Valid to RD or WR Low
t_AVRDL 4t_CLK - 130
ns
23 Data Valid to WR Going Low
t_DVWRL
t_CLK - 60
ns
24 ^{Data Valid to WR High}
at 12MHz
at 16MHz
t_DVWRH
7t_CLK - 150
7t_CLK - 90
ns
25 Data Valid After WR High
26 RD Low to Address Float
t_WRHDV
t_CLK - 50
ns
t_RDLAZ
0
ns
27 _{RD or WR High to ALE High}
t_RDHALH
t_CLK - 40 t_CLK + 50
ns
13 of 26