DS5000FP_1 Datasheet, PDF (18/22 Pages) Dallas Semiconductor – Soft Microprocessor Chip

DS5000FP
BYTE-WIDE ADDRESS/DATA BUS TIMING
AC CHARACTERISTICS
(T_A = 0°C to +70°C; V_CC = 5V ± 5%)
#
PARAMETER
SYMBOL MIN
MAX UNITS
56 _{Delay to Embedded Address Valid from CE1}
Low During Opcode Fetch
t_CE1LPA
20
ns
57 _{CE1 or CE2 Pulse Width}
t_CEPW
4t_CLK-15
ns
58 _{Embedded Address Hold after CE1 High} t_CE1HPA
2t_CLK-20
ns
During Opcode Fetch
59 _{Embedded Data Setup to CE1 High During} t_OVCE1H 1t_CLK+40
ns
Opcode Fetch
60 _{Embedded Data Hold after CE1 High During} t_CE1HOV
10
ns
Opcode Fetch
61 _{Embedded Address Hold after CE1 or CE2} t_CEHDA
4t_CLK-30
ns
High During MOVX
62 _{Delay from Embedded Address Valid to CE1} t_CELDA
4t_CLK-25
ns
or CE2 Low During MOVX
63 _{Embedded Data Hold Setup to CE1 or CE2} t_DACEH
1t_CLK+40
ns
High During MOVX (read)
64 _{Embedded Data Hold after CE1 or CE2 High} t_CEHDV
10
ns
During MOVX (read)
65 _{Embedded Address Valid to R/ W Active} t_AVRWL
3t_CLK-35
ns
During MOVX (write)
66 _{Delay from R/ W Low to Valid Data Out} t_RWLDV
20
ns
During MOVX (write)
67 _{Valid Data Out Hold Time from CE1 or CE2} t_CEHDV
1t_CLK-15
ns
High
68 _{Valid Data Out Hold Time from R/ W High} t_RWHDV
0
ns
69 _{Write Pulse Width (R/ W low time)}
t_RWLPW
6t_CLK-20
ns
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