DS5000FP_1 Datasheet, PDF (11/22 Pages) Dallas Semiconductor – Soft Microprocessor Chip

AC CHARACTERISTICS: EXPANDED
BUS MODE TIMING SPECIFICATIONS
#
PARAMETER
1 Oscillator Frequency
2 ALE Pulse Width
3 Address Valid to ALE Low
4 Address Hold After ALE Low
5 ALE Low to Valid Instr. In
@ 12MHz
@ 16MHz
6 _{ALE Low to PSEN Low}
7 _{PSEN Pulse Width}
8 _{PSEN Low to Valid Instr. In}
@ 12 MHz
@ 16 MHz
9 _{Input Instr. Hold after PSEN Going High}
10 _{Input Instr. Float after PSEN Going High}
11 _{Address Hold after PSEN Going High}
12 Address Valid to Valid Instr. In @ 12MHz
@ 16MHz
13 _{PSEN Low to Address Float}
14 RD Pulse Width
15 _{WR Pulse Width}
16 RD Low to Valid Data In
@ 12MHz
@ 16MHz
17 Data Hold after RD High
18 Data Float after RD High
19 ALE Low to Valid Data In
@ 12MHz
@ 16MHz
20 Valid Addr. to Valid Data In @ 12 MHz
@ 16 MHz
21 _{ALE Low to RD or WR Low}
22 _{Address Valid to RD or WR Low}
23 _{Data Valid to WR Going Low}
24 _{Data Valid to WR High}
@ 12MHz
@ 16MHz
25 _{Data Valid after WR High}
26 RD Low to Address Float
27 _{RD or WR High to ALE High}
DS5000FP
(T_A = 0°C to +70°C; V_CC = 5V ± 5%)
SYMBOL MIN
MAX UNITS
1/t_CLK
1.0
16
MHz
t_ALPW
2t_CLK -40
ns
t_AVALL
t_CLK -40
ns
t_AVAAV
t_CLK -35
ns
t_ALLVI
4t_CLK -150
ns
4t_CLK -90
ns
t_ALLPSL
t_CLK -25
ns
t_PSPW
3t_CLK -35
ns
t_PSLVI
3t_CLK -150
ns
3t_CLK -90
ns
t_PSIV
0
ns
t_PSIX
t_CLK -20
ns
t_PSAV
t_CLK -8
ns
t_AVVI
5t_CLK -150
ns
5t_CLK -90
ns
t_PSLAZ
0
ns
t_RDPW
6t_CLK -100
ns
t_WRPW
6t_CLK -100
ns
t_RDLDV
5t_CLK -165
ns
5t_CLK -105
ns
t_RDHDV
0
ns
t_RDHDZ
2t_CLK -70
ns
t_ALLVD
8_CLK -150
ns
8t_CLK -90
ns
t_AVDV
9t_CLK -165
ns
9t_CLK -105
ns
t_ALLRDL
3t_CLK -50 3t_CLK +50
ns
t_AVRDL
4t_CLK -130
ns
t_DVWRL
t_CLK -60
ns
t_DVWRH 7t_CLK -150
ns
7t_CLK -90
ns
t_WRHDV
t_CLK -50
ns
t_RDLAZ
0
ns
t_RDHALH
t_CLK -40
t_CLK +50
ns
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