DS21Q41B Datasheet, PDF (18/61 Pages) Dallas Semiconductor – Quad T1 Framer

CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
TESE
ODF
RSAO TSCLKM RSCLKM RESE
PLB
DS21Q41B
(LSB)
FLB
SYMBOL
TESE
ODF
RSAO
POSITION NAME AND DESCRIPTION
CCR1.7
Transmit Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
CCR1.6
Output Data Format.
0=bipolar data at TPOS and TNEG
1=NRZ data at TPOS; TNEG=0
CCR1.5
Receive Signaling All ones.
0=allow robbed signaling bits to appear at RSER
1=force all robbed signaling bits at RSER to 1
TSCLKM
CCR1.4
TSYSCLK Mode Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
RSCLKM
CCR1.3
RSYSCLK Mode Select.
0=if RSYSCLK is 1.544 MHz
1=if RSYSCLK is 2.048 MHz
RESE
CCR1.2
Receive Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
PLB
CCR1.1 Payload Loopback.
0=loopback disabled
1=loopback enabled
FLB
CCR1.0 Framer Loopback.
0=loopback disabled
1=loopback enabled
PAYLOAD LOOPBACK
When CCR1.1 is set to a one, the DS21Q41B will be forced into Payload LoopBack (PLB). Normally,
this loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS21Q41B
will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back; they are
reinserted by the DS21Q41B. When PLB is enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.
2. All of the receive side signals will continue to operate normally.
.
3. The TCHCLK and TCHBLK signals are forced low.
4. Data at the TSER pin is ignored.
5. The TLCLK signal will become synchronous with RCLK instead of TCLK.
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