DS87C520 Datasheet, PDF (12/45 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Micro

DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.
The on-chip data area is software selectable using 2 bits in the Power Management Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to
reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0 (PMR.0).
They have the following operation:
Table 2. Data Memory Access Control
DME1
0
0
1
1
DME0
0
1
0
1
DATA MEMORY ADDRESS
MEMORY FUNCTION
0000h–FFFFh
0000h–03FFh
0400h–FFFFh
Reserved
0000h–03FFh
0400h–FFFBh
FFFCh
FFFDh–FFFFh
External data memory (default condition)
Internal SRAM data memory
External data memory
Reserved
Internal SRAM data memory
Reserved—no external access
Read access to the status of lock bits
Reserved—no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of
the security lock bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.
Note: After internal MOVX SRAM has been initialized, changing the DME0/1 bits has no effect on the
contents of the SRAM.
STRETCH MEMORY CYCLE
The DS87C520/DS83C520 allow software to adjust the speed of off-chip data memory access. The
microcontrollers can perform the MOVX in as few as two instruction cycles. The on-chip SRAM uses
this speed and any MOVX instruction directed internally uses two cycles. However, the time can be
stretched for interface to external devices. This allows access to both fast memory and slow memory or
peripherals with no glue logic. Even in high-speed systems, it may not be necessary or desirable to
perform off-chip data memory access at full speed. In addition, there are a variety of memory-mapped
peripherals such as LCDs or UARTs that are slow.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
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