DS5002FP Datasheet, PDF (11/25 Pages) Dallas Semiconductor – Secure Microprocessor Chip

DS5002FP Secure Microprocessor Chip
PIN DESCRIPTION
PIN
11, 9, 7, 5,
1, 79, 77,
75
15, 17, 19,
21, 25, 27,
29, 31
49, 50, 51,
56, 58, 60,
64, 66
36
38
39
40
41
44
45
46
34
70
47, 48
52
13
12
54
16, 8, 18,
80, 76, 4, 6,
20, 24, 26,
28, 30, 33,
35, 37
71, 69, 67,
65,
61, 59, 57,
55
10
74
2
63
NAME
P0.0–P0.7
P1.0–P1.7
P2.0–P2.7
P3.0 RXD
P3.1 TXD
P3.2 INT0
P3.3 INT1
P3.4 T0
P3.5 T1
P3.6 WR
P3.7 RD
RST
ALE
XTAL2, XTAL1
GND
VCC
VCCO
VLI
BA14–0
BD7–0
R/W
CE1
CE2
CE3
FUNCTION
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
General-Purpose I/O Port 1
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART.
This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART.
This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
General-Purpose I/O Port Pin. Also serves as the write strobe for Expanded bus operation.
General-Purpose I/O Port Pin. Also serves as the read strobe for Expanded bus operation.
Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled
down internally so this pin can be left unconnected if not used. An RC power-on reset circuit
is not needed and is not recommended.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on
port 0. This pin is normally connected to the clock input on a ’373 type transparent latch.
XTAL1, XTAL 2. Used to connect an external crystal to the internal oscillator. XTAL1 is the
input to an inverting amplifier and XTAL2 is the output.
Logic Ground
VCC - +5V
VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on the
level of VCC. When power is above the lithium input, power is drawn from VCC. The lithium cell
remains isolated from a load. When VCC is below VLI, the VCCO switches to the VLI source.
VCCO should be connected to the VCC pin of an SRAM.
Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than VLIMAX
as shown in the electrical specifications. Nominal value is +3V.
Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed data bus
(BD7–0) to access NV SRAM. Decoding is performed using CE1 through CE4 . Therefore,
BA15 is not actually needed. Read/write access is controlled by R/ W . BA14–0 connect
directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are
unconnected. If a 128k SRAM is used, the micro converts CE2 and CE3 to serve as A16 and
A15, respectively.
Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on CE1
and CE2. Read/write access is controlled by R/W. D7–0 connect directly to an SRAM, and
optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It is
controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-wide
bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed. It remains in a
logic-high inactive state when VCC falls below VLI.
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, the micro converts CE2
into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when VCC
falls below VLI.
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE3
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