DS1385 Datasheet, PDF (10/20 Pages) Dallas Semiconductor – RAMified Real Time Clock 4K x 8

DS1385/DS1387
AM it changes to 1:00:00 AM. These special updates do
not occur when the DSE bit is a zero. This bit is not af-
fected by internal functions.
REGISTER C
MSB
BIT 7 BIT 6 BIT 5
IRQF PF
AF
BIT 4
UF
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a
one when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
i.e., IRQF = (PF • PIE) + (AF • AIE) + (UF • UIE)
Any time the IRQF bit is a one, the IRQ pin is driven low.
All flag bits are cleared after Register C is read by the
program.
PF – The Periodic Interrupt Flag (PF) is a read–only bit
which is set to a one when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0
bits establish the periodic rate. PF is set to a one inde-
pendent of the state of the PIE bit. When both PF and
PIE are ones, the IRQ signal is active and will set the
IRQF bit. The PF bit is cleared by a software read of
Register C.
AF – A one in the Alarm Interrupt Flag (AF) bit indicates
that the current time has matched the alarm time. If the
AIE bit is also a one, the IRQ pin will go low and a one will
appear in the IRQF bit. A read of Register C will clear
AF.
UF – The Update Ended Interrupt Flag (UF) bit is set af-
ter each update cycle. When the UIE bit is set to one, the
one in UF causes the IRQF bit to be a one which will as-
sert the IRQ pin. UF is cleared by reading Register C.
BIT 3 THROUGH BIT 0 – These are reserved bits of the
status Register C. These bits always read zero and can-
not be written.
REGISTER D
MSB
BIT 7 BIT 6 BIT 5
VRT
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
VRT – The Valid RAM and Time (VRT) bit is set to the
one state by Dallas Semiconductor Corporation prior to
shipment. This bit is not writable and should always be a
one when read. If a zero is ever present, an exhausted
internal lithium energy source is indicated and both the
contents of the RTC data and RAM data are question-
able.
BIT 6 THROUGH BIT 0 – The remaining bits of Register
D are reserved and not usable. They cannot be written
and, when read, they will always read zero.
4K X 8 RAM
The DS1385/DS1387 provides 4K x 8 of on–chip SRAM
which is controlled as nonvolatile storage sustained
from a lithium battery. On power–up, the RAM is taken
out of write–protect status by the internal power OK sig-
nal (POK) generated from the write protect circuitry.
The POK signal becomes active at 4.25 volts (typical).
The on–chip 4K x 8 nonvolatile SRAM is accessed via
the eight multiplexed address/data lines AD7–AD0. Ac-
cess to the SRAM is controlled by three on–chip latch
registers. Two registers are used to hold the SRAM ad-
dress and the third register is used to hold read/write
data. The SRAM address space is from 000H to FFFH.
Four control signals, AS0, AS1, OER, and WER, are
used to access the 4K x 8 SRAM. The address latches
are loaded from the address/data bus in response to ris-
ing edge signals applied to the Address Strobe 0 (AS0)
and Address Strobe 1 (AS1) signals. AS0 is used to
latch the lower 8–bits of address, and AS1 is used to
latch the upper 4–bits of address. It is necessary to
meet the setup and hold times given in the Electrical
Specifications with valid address information in order to
properly latch the address. If the upper or lower order
address is correct from a prior cycle, it is not necessary
to repeat the address latching sequence.
A write operation requires valid data to be placed on the
bus (AD7–AD0) followed by the activation of the Write
Enable RAM (WER) line. Data on the bus will be written
to the RAM provided that the write timing specifications
are met. During a read cycle, the Output Enable RAM
(OER) signal is driven active. Data from the RAM will
become valid on the bus provided that the RAM read ac-
cess timing specifications are met. The WER and OER
signals should never be active at the same time. In addi-
tion, access to the clock/calendar registers and user
RAM (via CS) must not be attempted when the 4K x 8
RAM is being accessed. The RAM is enabled when ei-
ther WER or OER is active. CS is only used for the ac-
cess of the clock calendar registers (including the ex-
tended Dallas registers) and the 50–bytes of user RAM.
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