DS12887A Datasheet, PDF (10/19 Pages) Maxim Integrated Products – Real-Time Clock

DS5000(T)
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
# PARAMETER
SYMBOL
1 Oscillator Frequency
2 ALE Pulse Width
3 Address Valid to ALE Low
4 Address Hold After ALE Low
5 ALE Low to Valid Instr. In
@12 MHz
@16 MHz
1/t_CLK
t_ALPW
t_AVALL
t_AVAAV
t_ALLVI
6 ALE Low to PSEN Low
7 PSEN Pulse Width
8 PSEN Low to Valid Instr. In @12 MHz
@16 MHz
t_ALLPSL
t_PSPW
t_PSLVI
9 Input Instr. Hold after PSEN Going High
10 Input Instr. Float after PSEN Going High
11 Address Hold after PSEN Going High
12 Address Valid to Valid Instr. In @12 MHz
@16 MHz
13 PSEN Low to Address Float
14 RD Pulse Width
15 WR Pulse Width
16 RD Low to Valid Data In
@12 MHz
@16 MHz
17 Data Hold after RD High
18 Data Float after RD High
19 ALE Low to Valid Data In
@12 MHz
@16 MHz
20 Valid Addr. to Valid Data In @12 MHz
@16 MHz
21 ALE Low to RD or WR Low
22 Address Valid to RD or WR Low
23 Data Valid to WR Going Low
24 Data Valid to WR High
@12 MHz
@16 MHz
t_PSIV
t_PSIX
t_PSAV
t_AVVI
t_PSLAZ
t_RDPW
t_WRPW
t_RDLDV
t_RDHDV
t_RDHDZ
t_ALLVD
t_AVDV
t_ALLRDL
t_AVRDL
t_DVWRL
t_DVWRH
25 Data Valid after WR High
26 RD Low to Address Float
27 RD or WR High to ALE High
t_WRHDV
t_RDLAZ
t_RDHALH
(t_A = 0°C to70°C; V_CC = 5V + 5%)
MIN
MAX
UNITS
1.0
16
MHz
2t_CLK –40
ns
t_CLK –40
ns
t_CLK –35
ns
4t_CLK –150
ns
4t_CLK –90
ns
t_CLK –25
ns
3t_CLK –35
ns
3t_CLK –150
ns
3t_CLK –90
ns
0
ns
t_CLK –20
ns
t_CLK –8
ns
5t_CLK –150
ns
5t_CLK –90
ns
0
ns
6t_CLK –100
ns
6t_CLK –100
ns
5t_CLK –165
ns
5t_CLK –105
ns
0
ns
2t_CLK –70
ns
8_CLK –150
ns
8t_CLK –90
ns
9t_CLK –165
ns
9t_CLK –105
ns
3t_CLK –50 3t_CLK +50
ns
4t_CLK –130
ns
t_CLK –60
ns
7t_CLK –150
ns
7t_CLK –90
ns
t_CLK –50
ns
0
ns
t_CLK –40
t_CLK +50
ns
021998 10/19