MB9B160L Datasheet, PDF (97/118 Pages) Cypress Semiconductor – 32-Bit ARM® Cortex® - M4F FM4 Microcontroller

MB9B160L Series
12.4.13 I²C Timing
Typical Mode, High-speed Mode
Parameter
Symbol Conditions
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
FSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
Noise filter
tSP
CL = 30 pF,
R = (Vp/IOL)*¹
2 MHz ≤
tCYCP<40 MHz
40 MHz ≤
tCYCP<60 MHz
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
tCYCP<100 MHz
100 MHz ≤
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
tCYCP<180 MHz
Typical Mode
Min
Max
0
100
4.0
-
4.7
-
4.0
-
4.7
-
0
3.45*²
250
-
4.0
-
4.7
-
2tCYCP*⁴
-
4tCYCP*⁴
-
6tCYCP*4
-
8tCYCP*⁴
-
10tCYCP*⁴
-
12tCYCP*⁴
-
14tCYCP*⁴
-
16tCYCP*⁴
-
(VCC = 2.7V to 5.5V, VSS = 0V)
High-speed Mode
Min
Max
Unit Remarks
0
400
kHz
0.6
-
μs
1.3
-
μs
0.6
-
μs
0.6
-
μs
0
0.9*³
μs
100
-
ns
0.6
-
μs
1.3
-
2tCYCP*⁴
-
4tCYCP*⁴
-
6tCYCP*⁴
-
8tCYCP*⁴
-
10tCYCP*⁴
-
12tCYCP*⁴
-
14tCYCP*⁴
-
16tCYCP*⁴
-
μs
ns
ns
ns
ns
*5
ns
ns
ns
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A high-speed mode I²C bus device can be used on a typical mode I²C bus system as long as the device satisfies the requirement
of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I²C is connected to, see "8. Block Diagram" in this data sheet.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
Document Number: 002-04976 Rev.*A
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