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MB9B160L Datasheet, PDF (3/118 Pages) Cypress Semiconductor – 32-Bit ARM® Cortex® - M4F FM4 Microcontroller | |||
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MB9B160L Series
Quadrature Position/Revolution Counter (QPRC) (1
channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
ï®The detection edge of the three external event input pins AIN,
BIN, and ZIN is configurable.
ï®16-bit position counter
ï®16-bit revolution counter
ï®Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
ï® Free-running
ï®Periodic (=Reload)
ï® One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
ï®External interrupt input pin: Max 16 pins
ï®Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
ï®CCITT CRC16 Generator Polynomial: 0x1021
ï®IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
ï®Main clock:
4 MHz to 48 MHz
ï®Sub Clock:
32.768 kHz
ï®High-speed internal CR Clock: 4 MHz
ï®Low-speed internal CR Clock: 100 kHz
ï®Main PLL Clock
[Resets]
ï®Reset requests from INITX pin
ï®Power on reset
ï®Software reset
ï®Watchdog timers reset
ï®Low voltage detector reset
ï®Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
ï®External OSC clock failure (clock stop) is detected, reset is
asserted.
ï®External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
ï®LVD1: error reporting via interrupt
ï®LVD2: auto-reset operation
Low-power Consumption Mode
Six low-power consumption modes are supported.
ï® SLEEP
ï® TIMER
ï® RTC
ï® STOP
ï®Deep standby RTC (selectable from with/without RAM
retention)
ï®Deep standby stop (selectable from with/without RAM
retention)
Document Number: 002-04976 Rev.*A
Page 3 of 118
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