CYFB0072V Datasheet, PDF (9/27 Pages) Cypress Semiconductor – 72-Mbit Video Frame Buffer

CYFB0072V
Table 2. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN LD WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
0
1
 First rising edge
X
because both LD and
WEN are low
X
Parallel write to first register
1
0
0
1  Second rising edge
X
X
Parallel write to second register
1
0
0
1  Third rising edge
X
X
Parallel write to third register
1
0
0
1  Fourth rising edge
X
X
Parallel write to fourth register
1
0
0
1

X
X

1
0
0
1

X
X

1
0
0
1

X
X

1
0
0
1  Tenth rising edge
X
X
Parallel write to tenth register
1
0
0
1  Eleventh rising edge
X
X
Parallel write to first register
(roll back)
1
0
1
0
X
 First rising edge since
X
Parallel read from first register
both LD and REN are
low
1
0
1
0
X
 Second rising edge
X
Parallel read from second
register
1
0
1
0
X
 Third rising edge
X
Parallel read from third register
1
0
1
0
X
 Fourth rising edge
X
Parallel read from fourth
register
1
0
1
0
X

X

1
0
1
0
X

X

1
0
1
0
X

X

1
0
1
0
X
 Tenth rising edge
X
Parallel read from tenth
register
1
0
1
0
X
 Eleventh rising edge
X
Parallel read from first register
(roll back)
1
X
1
1
X
X
X
No operation
X
1
0
X
 Rising edge
X
X
Write to Frame Buffer memory
X
1
X
0
X
 Rising edge
X
Read from Frame Buffer
memory
0
0
X
1
X
X
X
Illegal operation
Document Number: 001-88646 Rev. *A
Page 9 of 27