CYFB0072V Datasheet, PDF (1/27 Pages) Cypress Semiconductor – 72-Mbit Video Frame Buffer

CYFB0072V
72-Mbit Video Frame Buffer
72-Mbit Video Frame Buffer
Features
■ Memory organization
❐ Density: 72-Mbit
❐ Organization: × 36
■ Up to 133-MHz clock operation ^[1]
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐ Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
■ Input and output enable control for write mask and read skip
operations
■ Empty & Full status flags
■ Flow-through mailbox register to send data from input to output
port, bypassing the Frame Buffer
■ Separate serial clock (SCLK) input for serial programming of
configuration registers
■ Master reset to clear entire Frame Buffer
■ Partial reset to clear data but retain programmable settings
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Functional Description
The Video Frame Buffer is a 72-Mbit memory device which
operates as a FIFO with a bus width of 36 bits. It has independent
read and write ports, which can be clocked up to 133 MHz. The
bus size of 36 bits enables a data throughput of 4.8 Gbps. The
device also offers a simple and easy-to-use interface to reduce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including video and image
processing or any system that needs buffering at high speeds
across different clock domains.
The functionality of the Video Frame Buffer is such that the data
is read out of the read port in the same sequence in which it was
written into the write port. If writes and inputs are enabled (WEN
& IE), data on the write port gets written into the device at the
rising edge of write clock. Enabling reads and outputs (REN &
OE) fetches data on the read port at every rising edge of read
clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio between read and write clock
is in the range of 0.5 to 2. Appropriate flags are set whenever the
device is empty or full.
The device also supports a flow-through mailbox register to
bypass the frame buffer memory
Note
1. For device operating at 150 MHz, Contact Sales.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88646 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 26, 2013