CY7C4261_05 Datasheet, PDF (9/18 Pages) Cypress Semiconductor – 16K/32K x 9 Deep Sync FIFOs

Switching Waveforms (continued)
Reset Timing^[16]
t_RS
RS
REN1,
REN2
t_RSS
t_RSS
WEN1
WEN2/LD ^[18]
t_RSS
EF,PAE
FF,PAF
Q_{0 -} Q₈
t_RSF
t_RSF
t_RSF
First Data Word Latency after Reset with Read and Write
WCLK
t_DS
D₀ –D₈
D₀(FIRST VALID WRITE)
D₁
WEN1
t_ENS
t_FRL ^[19]
WEN2
(if applicable)
RCLK
EF
REN1,
REN2
t_SKEW1
t_REF
CY7C4261
CY7C4271
t_RSR
t_RSR
t_RSR
OE = 1^[17]
OE = 0
D₂
D₃
D₄
[20]
t_A
t_A
Q₀ –Q₈
OE
t_OLZ
t_OE
D₀
D₁
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
19. When t_SKEW1 > minimum specification, t_FRL (maximum) = t_CLK + t_SKEW2. When t_SKEW2 < minimum specification, t_FRL (maximum) = either 2*t_CLK + t_SKEW1 or t_CLK
+ t_SKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06015 Rev. *C
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