CY7C4261_05 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 16K/32K x 9 Deep Sync FIFOs

16K/32K x 9 Deep Sync FIFOsCY7C4271CY7C4261
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
Features
• Pb-Free Packages Available
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — I_CC = 35 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
Logic Block Diagram D_0–8
Functional Description
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
Pin Configuration ^PLCC/LCC
Top View
WCLK WEN1 WEN2/LD
WRITE
CONTROL
WRITE
POINTER
RS
RESET
LOGIC
INPUT
REGISTER
RAM
ARRAY
16K x 9
32K x 9
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
EF
PAE
PAF
FF
THREE-STATE
OUTPUT REGISTER
OE
Q_0–8
READ
CONTROL
RCLK REN1 REN2
D₁
D₀
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 32 31 30
5
29
6
28
7
27
8 _CY7C4261 26
9
10
CY7C4271
25
24
11
23
12
22
13
21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
V_CC
Q₈
Q₇
Q₆
Q₅
TQFP
Top View
D₁
D₀
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
CY7C4261
21
5
CY7C4271 20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
V_CC
Q₈
Q₇
Q₆
Q₅
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06015 Rev. *C
Revised August 2, 2005