CY7C026A_12 Datasheet, PDF (9/21 Pages) Cypress Semiconductor – 16K x 16 Dual-Port Static RAM

CY7C026A
Switching Characteristics Over the Operating Range^[8] (continued)
Parameter
Description
BUSY TIMING^[15]
t_BLA
BUSY LOW from address match
t_BHA
BUSY HIGH from address mismatch
t_BLC
BUSY LOW from CE LOW
t_BHC
BUSY HIGH from CE HIGH
t_PS
Port setup for priority
t_WB
R/W HIGH after BUSY (Slave)
t_WH
R/W HIGH after BUSY HIGH (Slave)
t_BDD[16]
BUSY HIGH to data valid
INTERRUPT TIMING^[15]
t_INS
INT set time
t_INR
INT reset time
SEMAPHORE TIMING
t_SOP
t_SWRD
t_SPS
t_SAA
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
CY7C026A
-15
-20
Unit
Min
Max
Min
Max
–
15
–
20
ns
–
15
–
20
ns
–
15
20
ns
–
15
–
17
ns
5
–
5
–
ns
0
–
0
–
ns
13
–
15
–
ns
–
15
–
20
ns
–
15
–
20
ns
–
15
–
20
ns
10
–
10
–
ns
5
–
5
–
ns
5
–
5
–
ns
–
15
–
20
ns
Data Retention Mode
The CY7C026A is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V_CC to V_CC – 0.2 V.
2. CE must be kept between V_CC – 0.2 V and 70% of V_CC during
the power up and power down transitions.
3. The RAM can begin operation >t_RC after V_CC reaches the
minimum operating voltage (4.5 V).
Timing
V_CC
CE
Data Retention Mode
4.5 V
V_CC 2.0 V
4.5 V
t_RC
V_CC to V_CC – 0.2 V
VIH
Parameter
ICC_DR1
Test Conditions^[17]
At VCC_DR = 2 V
Max
1.5
Unit
mA
Notes
15. Test conditions used are Load 2.
16. t_BDD is a calculated parameter and is the greater of t_WDD–t_PWE (actual) or t_DDD–t_SD (actual).
17. CE = V_CC, V_in = GND to V_CC, T_A = 25 C. This parameter is guaranteed but not tested.
Document #: 38-06046 Rev. *G
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