CY7C026A_12 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 16K x 16 Dual-Port Static RAM

CY7C026A16K x 16 Dual-Port Static RAM
CY7C026A
16K x 16 Dual-Port Static RAM
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ 16K x 16 organization (CY7C026A)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15, and 20 ns
■ Low operating power
■ Active: I_CC = 180 mA (typical)
■ Standby: I_SB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
Logic Block Diagram
R/W_L
UB_L
■ Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Pin select for Master or Slave
■ Commercial and Industrial temperature ranges
■ Available in 100-pin thin quad plastic flatpack (TQFP)
■ Pb-free packages available
R/W_R
UB_R
CE_L
LB_L
OE_L
8
I/O_8L–I/O₁₅^[1_L^]
I/O_0L–I/O^[₇²_L^]
8
I/O
Control
I/O
Control
CE_R
LB_R
OE_R
8
I/O_8L–I/^[O^1]_15R
8
I/O_0L–I/O^[2]_7R
A_0L–A_13L
14
Address
Decode
True Dual-Ported
RAM Array
14
A_0L–A_13L
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[3]
INT_L
UB_L
LB_L
Notes
1. I/O₈–I/O₁₅ for x16 devices.
2. I/O₀–I/O₇ for x16 devices.
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
14
Decode
14
A_0R–A_13R
A_0R–A_13R
CE_R
OE_R
R/W_R
SEM_R
[3] _BUSYR
INT_R
UB_R
LB_R
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06046 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2011