CY7C008_05 Datasheet, PDF (9/19 Pages) Cypress Semiconductor – 64K/128K x 8/9 Dual-Port Static RAM

Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)^{[22, 23, 24]}
t_RC
ADDRESS
DATA OUT
t_AA
t_OHA
PREVIOUS DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)^{[22, 25, 26]}
CE
OE
DATA OUT
I_CC
CURRENT
I_SB
t_ACE
t_DOE
t_LZOE
t_LZCE
t_PU
Read Cycle No. 3 (Either Port)^{[22, 24, 25, 26]}
t_RC
ADDRESS
t_AA
CY7C008/009
CY7C018/019
DATA VALID
t_OHA
t_HZCE
t_HZOE
DATA VALID
t_PD
t_OHA
CE
DATA OUT
t_LZCE
t_ABE
t_ACE
t_LZCE
Notes:
22. R/W is HIGH for read cycles.
23. Device is continuously selected CE = V_IL. This waveform cannot be used for semaphore reads.
24. OE = V_IL.
25. Address valid prior to or coincident with CE transition LOW.
26. To access RAM, CE = V_IL, SEM = V_IH. To access semaphore, CE = V_IH, SEM = V_IL.
t_HZCE
Document #: 38-06041 Rev. *D
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