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CY7C008_05 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 64K/128K x 8/9 Dual-Port Static RAM | |||
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CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
⢠True Dual-Ported memory cells that allow simultaneous
access of the same memory location
⢠64K x 8 organization (CY7C008)
⢠128K x 8 organization (CY7C009)
⢠64K x 9 organization (CY7C018)
⢠128K x 9 organization (CY7C019)
⢠0.35-micron CMOS for optimum speed/power
⢠High-speed access: 12[1]/15/20 ns
⢠Low operating power
â Active: ICC = 180 mA (typical)
â Standby: ISB3 = 0.05 mA (typical)
⢠Fully asynchronous operation
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
CEL
⢠Automatic power-down
⢠Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
⢠On-chip arbitration logic
⢠Semaphores included to permit software handshaking
between ports
⢠INT flags for port-to-port communication
⢠Dual Chip Enables
⢠Pin select for Master or Slave
⢠Commercial and Industrial temperature ranges
⢠Available in 100-pin TQFP; Pb-Free packages available
CER
R/WR
CE0R
CE1R
OER
[2]
8/9
I/O0LâI/O7/8L
I/O
Control
I/O
Control
8/9
[2]
I/O0RâI/O7/8R
A0LâA[135]/16L
16/17
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
16/17
A0Râ[A3]15/16R
A0LâA[135]/16L
CEL
OEL
R/WL
SEML
BUSYL [4]
INTL
16/17
Notes:
1. See page 6 for Load Conditions.
2. I/O0âI/O7 for x8 devices; I/O0âI/O8 for x9 devices.
3. A0âA15 for 64K devices; A0âA16 for 128K.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
16/17
A0Râ[A3]15/16R
CER
OER
R/WR
SEMR
[4] BUSYR
INTR
Cypress Semiconductor Corporation ⢠198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Document #: 38-06041 Rev. *D
Revised September 6, 2005
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