CY62136ESL_13 Datasheet, PDF (9/16 Pages) Cypress Semiconductor – 2-Mbit (128 K x 16) Static RAM

CY62136ESL MoBL^®
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled ^{[23, 24, 25]}
t_WC
ADDRESS
CE
t_SCE
t_AW
t_HA
t_SA
WE
t_PWE
BHE/BLE
OE
DATA I/O
ADDRESS
CE
WE
BHE/BLE
t_BW
NOTE 26
t_SD
t_HD
t_HZOE
DATA_IN
Figure 7. Write Cycle 2: CE Controlled ^{[23, 24, 25]}
t_WC
t_SCE
t_SA
t_AW
t_HA
t_PWE
t_BW
OE
DATA I/O
NOTE 26
t_HZOE
t_SD
t_HD
DATA_IN
Notes
23.
The internal write
signals terminate
time of the memory is defined by the
a write by going INACTIVE. The data
overlap of WE, CE =
input setup and hold
Vtim_IL,inBgHaErearnedf/eorreBncLeEd=toVt_IhL.eAelldsgiegnoaf ltshaerseigAnCaTl ItVhaEt
to initiate a
terminates
write and
the write.
any
of
these
24. Data I/O is high impedance if OE = V_IH.
25. If CE goes HIGH simultaneously with WE = V_IH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-48147 Rev. *G
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