CY62136ESL_13 Datasheet, PDF (7/16 Pages) Cypress Semiconductor – 2-Mbit (128 K x 16) Static RAM

Switching Characteristics
Over the Operating Range
Parameter ^{[15, 16]}
Description
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle ^[19]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z ^[17]
OE HIGH to High Z ^{[17, 18]}
CE LOW to Low Z ^[17]
CE HIGH to High Z ^{[17, 18]}
CE LOW to power-up
CE HIGH to ower-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z ^[17]
BLE/BHE HIGH to High Z ^{[17, 18]}
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z ^{[17, 18]}
WE HIGH to Low Z ^[17]
CY62136ESL MoBL^®
45 ns
Unit
Min
Max
45
–
ns
–
45
ns
10
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
0
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
45
–
ns
35
–
ns
35
–
ns
0
–
ns
0
–
ns
35
–
ns
35
–
ns
25
–
ns
0
–
ns
–
18
ns
10
–
ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified I_OL/I_OH as shown in the Figure 2 on page 5.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
17. At any temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any device.
18. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high-impedance state.
19.
The internal write time of the memory is defined
signals can terminate a write by going inactive.
by the overlap
The data input
of WE, CE
setup and
=hoVld_IL,tiBmHinEg,
BmLuEstobreborethfe=reVn_{IcLe. dAltlositghneaelsdmgeusotf}
be active to initiate a write
the signal that terminates
and any of
the write.
these
Document Number: 001-48147 Rev. *G
Page 7 of 16