CY28510 Datasheet, PDF (9/13 Pages) SpectraLinear Inc – Peripheral I/O Clock Generator

CY28510
VDD_ALL
CLK
REF
2 .0 V
<1.2m sec
Figure 3. Power-up Signal Timing
CLK_STOP# Clarification
The CLK_STOP# signal is an active low input used for
synchronous stopping and starting the CLK output clocks
while the rest of the clock generator continues to function.
CLK_STOP# Assertion
When CLK_STOP# pin is asserted low, all CLK outputs will be
stopped after being sampled by two rising CLK internal clock
edges.
CLK_STOP#
CLK
CLK Internal
Figure 4. CLK_STOP# Assertion Waveforms
CLK_STOP# Deassertion
The deassertion of the CLK_STOP# signal will cause all CLK
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produced when the
clock resumes. The maximum latency from the deassertion to
active outputs is no more than 2 CLK clock cycles
CLK_STOP#
CLK
CLK Internal
Figure 5. CLK_STOP# Deassertion Waveforms
Document #: 38-07542 Rev. **
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