CY28510 Datasheet, PDF (1/13 Pages) SpectraLinear Inc – Peripheral I/O Clock Generator

510
CY28510
Features
• 15 33.27-MHz or 66.669-MHz clock outputs
• 1 REF 14.318 MHz
• Divide by 2, spread spectrum and output enable all se-
lectable on a per-output basis via I²C register bits
• Divide by 2 mode default values strappable on a
per-group basis
• Output Enable pin controls all outputs
Block Diagram
Peripheral I/O Clock Generator
• I²C Compatible Programmability With Block and Byte
Modes
• I²C Operates Up to 1MHz
• I²C Address Selection of D0, D2, D4 or D6
• 48 Pin SSOP Package
Pin Configuration
XIN
REF
PLL 1with
Spread
Spectrum
66MHz
CLK_STOP#
PLL 2 no
Spread
Spectrum
66MHz
(Group Frequency Select, 33 or 66MHz)
GFS0
SCLK
I2C
SDATA
ADDSEL(0:1)
GFS1
GFS2
GFS3
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
Mux
÷2
CLKG0_0
CLKG0_1
CLKG0_2
CLKG0_3
CLKG0_4
CLKG0_5
CLKG0_6
CLKG0_7
CLKG1_0
CLKG1_1
CLKG1_2
CLKG1_3
CLKG2_0
CLKG2_1
CLKG3
GFS3
1
REF 2
GFS0
3
VDDX
4
VSSX
5
XIN
6
XOUT
7
VDDC
8
ADDSEL0
9
ADDSEL1
10
VSSC
11
CLK_STOP#
12
SCLK
13
SDATA
14
GFS1
15
GFS2
16
OE
17
CLKG3
18
VDDQ3
19
VSSQ3
20
VSSQ2
21
CLKG2_1
22
CLKG2_0
23
VDDQ2
24
48
VDDQ0
47
CLKG0_0
46
CLKG0_1
45
VSSQ0
44
CLKG0_2
43
VDDQ0
42
VSSQ0
41
CLKG0_3
40
CLKG0_4
39
VDDQ0
38
CLKG0_5
37
CLKG0_6
36
CLKG0_7
35
VSSQ0
34
VDDQ1
33
CLKG1_0
32
CLKG1_1
31
VSSQ1
30
VDDQ1
29
CLKG1_2
28
CLKG1_3
27
VSSQ1
26
VDDA
25
VSSA
OE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07542 Rev. **
Revised April 28, 2003