CY28342 Datasheet, PDF (9/22 Pages) Cypress Semiconductor – High-performance SiS645/650 Pentium 4 Clock Synthesizer

CY28342
Byte 12: Watchdog Time Stamp Register (All bits are Read and Write functional)
Bit @Pup Name
Description
7
1
SRESET#/PCI_STP#. 1 = pin 12 is the input pin as PCI_STP# signal. 0 = pin 12 is the output pin
as SRESET# signal.
6
0
Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due
to Watchdog time-out only. 0 = selects frequency of existing H/W setting. 1 = selects frequency of
the second to last S/W setting (the software setting prior to the one that caused a system reboot).
5
0
WDTEST. For WD-Test, ALWAYS program to “0.”
4
0
WD Alarm. This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system
clears the WD time stamps (WD3:0).
3
0
WD3 These bits select the Watchdog Time Stamp Value. See Table 8.
2
0
WD2
1
0
WD1
0
0
WD0
Table 8. Watchdog Time Stamp Table
WD(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FUNCTION
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
Byte 13: Dial-a-Frequency Control Register N (All bits are Read and Write functional)^[5]
Bit
@Pup
7
0
Reserved.
6
0
N6, MSB
5
0
N5
4
0
N4
3
0
N3
2
0
N2
1
0
N3
0
0
N0, LSB
Note:
5. Byte 13 and Byte 14 should be Write together in every case.
Description
Document #: 38-07349 Rev. *A
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