CY28342 Datasheet, PDF (4/22 Pages) Cypress Semiconductor – High-performance SiS645/650 Pentium 4 Clock Synthesizer

CY28342
Pin Description (continued)^[2]
Pin
Name
PWR
I/O
Description
47
SDCLK
VDDSD O SDRAM Clock Output.
30,31
AGP (0:1) VDDAGP O AGP Clock Outputs. See Table 1 for frequencies and functionality.
48
VDDSD
PWR 3.3V power supply for SDRAM clock output.
29
VDDAGP
PWR 3.3V power supply for AGP clock output.
11
VDDZ
PWR 3.3V power supply for HyperZip clock output.
1
VDDR
PWR 3.3V power supply for REF clock output.
13,19
VDDP
PWR 3.3V power supply for PCI clock output.
42
VDDC
PWR 3.3V power supply for CPU clock output.
28
VDD48M
PWR 3.3V power supply for 48-MHz/24-MHz clock output.
36
VDDA
PWR 3.3V analog power supply.
18,24
VSSP
PWR GND for PCI clocks outputs.
41
VSSC
PWR GND for CPU clocks outputs.
8
VSSZ
PWR GND for HyperZip clocks outputs.
25
VSS48M
PWR GND for 48-MHz/24-MHz clocks outputs.
5
VSSR
PWR GND for REF clocks outputs.
46
VSSSD
PWR GND for SDRAM clocks outputs.
32
VSSAGP
PWR GND for AGP clocks outputs.
37
VSSA
PWR GND for analog.
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions such as
individual clock output buffers, etc., can be individually
enabled or disabled.
The registers associated with the SDI initializes to their default
setting upon power-up, and therefore the use of this interface
is optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
The clock driver serial protocol accepts byte Write, byte Read,
block Write, and block Read operations from the controller. For
a block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte Write and byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block Write and block Read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte Write and byte
Read protocol.
The slave receiver address is 11010010 (D2h).
Note:
2. PU = Internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 –1.8V, and HIGH = > 2.0V.
Document #: 38-07349 Rev. *A
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