CY27EE16ZE_04 Datasheet, PDF (9/17 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

CY27EE16ZE
Clock Output Settings
CLKSRC - Clock Output Crosspoint Switch Matrix
[44H(7..0)], [45H(7..0)], [46H(7..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint
switch matrix defines which source is attached to each
individual clock output. CLKSRC(2..0) is set in Registers 44H,
45H, and 46H. The remainder of registers 45H(3:1) and
46H(2:0) must be written with the values stated in the register
table when writing register values 45H(7:4), 45H(0), and
46H(7:3).
When DIV1N is divisible by 4, then CLKSRC(0,1,0) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1). When DIV1N is 6, then CLKSRC(0,1,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1).
When DIV2N is divisible by 4, then CLKSRC(1,0,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(1,0,0). When DIV2N is divisible by 8, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
CLKOE - Clock Output Enable Control [09H(7..0)]
Each clock output has its own output enable, CLKOE,
controlled by register 09H(7..0). To enable an output, set the
corresponding CLKOE bit to 1. CLKOE settings are in
Table 13.
Test, Reserved, and Blank Registers
Writing to any of the following registers will cause the part to
exhibit abnormal behavior:
[00H to 08H] – Reserved
[0AH to 0BH] – Reserved
[0DH to 0FH] –Reserved
[15H to 3FH] –Reserved
[43H] –Reserved
[48H to FFH] –Reserved
Table 11.Clock Output Settings – Clock Source CLKSRC[2:0]
CLKSRC2
0
0
0
0
1
1
1
1
CLKSRC1
0
0
1
1
0
0
1
1
CLKSRC0
Definition and Notes
0
Reference Input
1
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8
0
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
1
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
0
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
1
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
0
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
1
Reserved – Do not use
Table 12.CLKSRC Registers
Address
44H
45H
46H
D7
D6
D5
D4
D3
D2
D1
D0
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1
for CLOCK1 for CLOCK1 for CLOCK1 for CLOCK2 for CLOCK2 for CLOCK2 for CLOCK3 for CLOCK3
CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0
1
1
1
CLKSRC2
for CLOCK3 for CLOCK4 for CLOCK4 for CLOCK4
for CLOCK5
CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0
1
1
1
for CLOCK5 for CLOCK5 for CLOCK6 for CLOCK6 for CLOCK6
Table 13.CLKOE Bit Setting
Address
09H
D7
D6
D5
D4
D3
D2
D1
0
CLKOE for CLKOE for
0
CLKOE for CLKOE for CLKOE for CLKOE for
CLOCK6 CLOCK5
CLOCK4 CLOCK3 CLOCK2 CLOCK1
Document #: 38-07440 Rev. *C
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