CY27EE16ZE_04 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

CY27EE16ZE
1 PLL In-System Programmable Clock Generator
with Individual 16K EEPROM
Features
Benefits
• 18 kbits of EEPROM
16 kbits independent scratch
2 kbits dedicated to clocking functions
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers, and optional analog
VCXO, digital VCXO, spread spectrum for EMI reduction
• In system programmable through I²C Serial
Programming Interface (SPI). Both the SRAM and
non-volatile EEPROM memory bits are programmable
with the 3.3V supply
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V Operation (optional 2.5V outputs)
• 20-lead Exposed Pad, EP-TSSOP
Higher level of integration and reduced component count by
combining EEPROM and PLL. Independent EEPROM may be
used for scratch memory, or to store up to eight clock config-
urations.
High-performance PLL enables control of output frequencies
that are customizable to support a wide range of applications.
Familiar industry standard eases programming effort and
enables update of data stored in 16K EEPROM scratchpad
and 2K EEPROM clock control block while CY27EE16ZE is
installed in system.
Meets critical timing requirements in complex system designs.
Write Protect (WP pin) can be programmed to serve as an
analog control voltage for a VCXO.The VCXO function is still
available with a DCXO, or digitally controlled (through SPI)
crystal oscillator if the pin is functioning as WP.
Meets industry-standard voltage platforms.
Industry standard packaging saves on board space.
Part Number
CY27EE16ZE
Outputs
Input Frequency Range
Output Frequency Range
6 1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial} 80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.} 80 kHz –167 MHz (2.5V) {Commercial}
80 kHz – 150 MHz (2.5V) {Industrial}
Logic Block Diagram
XIN
XOUT
VCX/WP
PDM/OE
[I2C- SPI:]SCL
SDAT
OSC
Q
Φ
VCO
P
PLL
Clock
Configuration
8x2k EEPROM
Memory Array
VDD VSS
VDDL VSSL
AVDD AVSS
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLOCK1
CLOCK2
CLOCK3
CLOCK4
CLOCK5
CLOCK6
Pin Configurations
CY27EE16ZE
20-pin EP-TSSOP
XIN 1
VDD 2
CLOCK6 3
AVDD 4
SDAT 5
AVSS 6
VSSL 7
CLOCK1 8
CLOCK2 9
OE/PDM 10
20 XOUT
19 VDD
18 CLOCK5
17 VCXO/WP
16 VSS
15 CLOCK4
14 VDDL
13 SCL
12 CLOCK3
11 VDDL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07440 Rev. *C
Revised December 21, 2004