CY8C3245AXI-158 Datasheet, PDF (84/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
11.5 Analog Peripherals
Specifications are valid for –40 °C  T_A  85 °C and T_J  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 Delta-sigma ADC
Unless otherwise specified, operating conditions are:
 Operation in continuous sample mode
 fclk = 6.144 MHz
 Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
 Unless otherwise specified, all charts and graphs show typical values
Table 11-19. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Resolution
Conditions
Number of channels, single ended
Number of channels, differential
Differential pair is formed using a
pair of GPIOs.
Monotonic
Yes
Ge
Gain error
Buffered, buffer gain = 1, Range =
±1.024 V, 25 °C
Gd
Gain drift
Buffered, buffer gain = 1, Range =
±1.024 V
Vos
Input offset voltage
Buffered, 12-bit mode
TCVos
Temperature coefficient, input offset
voltage
Input voltage range, single ended^[45]
Buffer gain = 1, 12-bit,
Range = ±1.024 V
Input voltage range, differential unbuf-
fered^[45]
INL12
DNL12
INL8
DNL8
Input voltage range, differential,
buffered^[45]
Integral non linearity^[45]
Differential non linearity^[45]
Integral non linearity^[45]
Differential non linearity^[45]
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Rin_Buff ADC input resistance
Input buffer used
Rin_ADC12 ADC input resistance
Input buffer bypassed, 12 bit,
Range = ±1.024 V
Rin_ExtRef ADC external reference input resistance
Vextref
ADC external reference input voltage, see
also internal reference in Voltage
Pins P0[3], P3[2]
Reference on page 86
Current Consumption
I_{DD_12}
I_BUFF
I_DDA + I_DDD current consumption, 12 bit^[45] 192 ksps, unbuffered
Buffer current consumption^[45]
Min
8
–
–
–
–
–
–
–
V_SSA
V_SSA
Typ
Max Units
–
12
bits
–
No. of
GPIO
–
–
No. of
GPIO/2
–
–
–
–
–
±0.2
%
–
50
ppm/°
C
–
±0.1
mV
–
1
µV/°C
–
V_DDA
V
–
V_DDA
V
V_SSA
–
V_DDA – 1 V
–
–
–
–
–
–
–
–
10
–
±1
LSB
±1
LSB
±1
LSB
±1
LSB
–
M
–
148^[46]
–
k
–
70^{[46, 47]}
–
k
0.9
–
1.3
V
–
–
1.95
mA
–
–
2.5
mA
Notes
45. Based on device characterization (not production tested).
46. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
47. Recommend an external reference device with an output impedance <100 Ω, for example, the LM185/285/385 family. A 1-µF capacitor is recommended. For more
information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations.
Document Number: 001-56955 Rev. *Y
Page 84 of 128