S6J312A Datasheet, PDF (81/139 Pages) Cypress Semiconductor – 32-Bit Traveo™ Family Microcontroller Datasheet

S6J3120 Series
(5-1-2) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, Vcc=DVcc=5.0 V ±10%, VSS=DVSS=AVSS=0.0 V)
Parameter
Symb
ol
Pin Name
Conditions
Value
Min
Max
Unit Remarks
Serial clock
cycle time
tSCYC
SCK0 to SCK4,
SCK8 to SCK12
Master
4tCLK_LCPnA*
-
ns
SCK0 to SCK4,
mode
SCK ↑ → SOT
delay time
SCK8 to SCK12,
(CL=50pF,
tSHOVI
SOT0 to SOT4,
-30
IOL=-2mA,
SOT8 to SOT12
IOH=2mA),
Valid SIN → SCK ↓
setup time
tIVSLI
SCK0 to SCK4,
SCK8 to SCK12,
(CL=20pF,
30
SIN0 to SIN4,
IOL=-1mA,
SCK ↓ → Valid SIN
hold time
tSLIXI
SIN8 to SIN12
IOH=1mA)
0
+30
ns
-
ns
-
ns
Serial clock
"H" pulse width
tSHSL
SCK0 to SCK4,
tCLK_LCPnA* +10
-
ns
Serial clock
"L" pulse width
tSLSH
SCK8 to SCK12
2tCLK_LCPnA* -10
-
ns
SCK0 to SCK4,
Slave
SCK ↑ → SOT
delay time
tSHOVE
SCK8 to SCK12,
SOT0 to SOT4,
mode
(CL=50pF,
-
SOT8 to SOT12
IOL=-2mA,
Valid SIN → SCK ↓
setup time
tIVSLE
SCK0 to SCK4,
SCK8 to SCK12,
IOH=2mA),
10
SIN0 to SIN4,
(CL=20pF,
SCK ↓ → Valid SIN
hold time
tSLIXE
SIN8 to SIN12
IOL=-1mA,
20
IOH=1mA)
SCK0 to SCK4,
SCK fall time
tF
-
SCK8 to SCK12
30
ns
-
ns
-
ns
5
ns
SCK rise time
SCK0 to SCK4,
tR
SCK8 to SCK12
*: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
-
5
ns
Notes:
− This is the AC characteristic in CLK synchronized mode.
− CL is the load capacitance applied to pins during testing.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04863 Rev.*B
Page 81 of 139