S6J312A Datasheet, PDF (1/139 Pages) Cypress Semiconductor – 32-Bit Traveo™ Family Microcontroller Datasheet

S6J3120 Series
32-Bit Traveo™ Family
Microcontroller Datasheet
This section provides an overview of the S6J3120 series. The S6J3120 series is a set of 32-bit microcontrollers designed for
in-vehicle use. It uses the ARM^® Cortex-R5 CPU as a CPU.
Features
This section explains the features of the S6J3120 series.
Cortex-R5 Core
This section explains the Cortex-R5 CPU core.
 ARM^® Cortex^®-R5
 32-bit ARM architecture
• 2-instruction issuance super scalar
• 8-stage pipeline
 ARMv7/Thumb^®-2 instruction set
 MPU (memory protection) equipped
• 16-area support
 ECC support for the TCM ports for RAM
1-bit error correction and 2-bit error detection
(SEC-DED)
 TCM ports
2 TCM ports
• ATCM port
• BTCM port (B0TCM, B1TCM)
 Caches
• Instruction cache 16 KB
• Data cache 16 KB
 VIC port
Low latency interrupt
 AXI master interface
64-bit AXI interface (instruction/data access)
32-bit AXI interface (I/O access)
 AXI slave interface
64-bit AXI interface (TCM port access)
 ETM-R5 trace
Peripheral Functions
This section explains peripheral functions.
Clock generation
 Main clock oscillation (4 MHz)
 No sub clock oscillation
 CR oscillation (100 kHz)
 CR oscillation (4 MHz)
Built-in Flash memory size
 Program: 1024 K + 64 KB (S6J312AHzC*)/768 K + 64 KB
(S6J3129HzC*)/512 K + 64 KB (S6J3128HzC*)
 *z: A/B
 Work: 112 KB (S6J312AHzC*)/ 112 KB
(S6J3129HzC*)/112 KB (S6J3128HzC*)
 *z: A/B
Built-in RAM size
 TCRAM 64 KB(S6J312AHzC*)/ 48 KB(S6J3129HzC*)/32
KB(S6J3128HzC*)
 System SRAM 16 KB (S6J312AHzC*)/ 16 KB
(S6J3129HzC*)/ 16 KB (S6J3128HzC*)
 Backup RAM 8 KB (S6J312AHzC*)/ 8 KB
(S6J3129HzC*)/8 KB (S6J3128HzC*)
 *z: A/B
General-purpose ports: 112 channels (S6J312AHzC*)/ 112
channels (S6J3129HzC*)/ 112 channels (S6J3128HzC*)
 *z: A/B
External bus interface
 24-bit address, 16bit data
DMA controller
 Up to 16 channels can be activated simultaneously.
A/D converter (successive approximation type)
 12-bit resolution, 2 units mounted: Max 50 channels (22
channels + 28 channels)(S6J312AHzC*)/ Max 50 channels
(22 channels + 28 channels)(S6J3129HzC*)/ Max 50
channels (22 channels + 28 channels)(S6J3128HzC*)
 *z: A/B
External interrupt input: 16 channels
 Level ("H"/"L") and edge (rising/falling) can be detected.
Multi-function serial (transmission and reception FIFOs
mounted) :Max 10 channels(S6J312AHzC*)/ Max 10
channels(S6J3129HzC*)/ Max 10 channels(S6J3128HzC*)
 *z: A/B
<I²C>
 Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
 Standard mode (Max. 100kbps) is supported only.
 DMA transfer is supported.
<UART (asynchronous serial interface) >
 Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
 Parity check can be enabled/disabled.
 Built-in dedicated baud rate generator
 An external clock can be used as a transfer clock.
 Parity, frame, overrun error detection functions are
available.
 DMA transfer is supported.
Cypress Semiconductor Corporation
Document Number: 002-04863 Rev.*B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised June 16, 2016