W191 Datasheet, PDF (8/10 Pages) SpectraLinear Inc – Skew Controlled SDRAM Buffer

PRELIMINARY
Signaling from System Core Logic
Start Condition
Slave Address
(First Byte)
Command Code
(Second Byte)
Byte Count
(Third Byte)
SDATA
MSB
LSB
11010010
MSB
LSB
MSB
MSB
Last Data Byte
(Last Byte)
Stop Condition
LSB
SCLOCK
1 2 3 4 5 6 7 8A1 2 3 4 5 6 7 8A 1 2 3 4
1 2 3 4 5 6 7 8A
SDATA
Signaling by Clock Device
Acknowledgment Bit
from Clock Device
Figure 4. Serial Data Bus Write Sequence
W191
SDATA
SCLOCK
t_STHD
t_LOW
t_R
t_HIGH
t_F
t_DSU
t_DHD
t_SP
t_SPSU
t_STHD
Figure 5. Serial Data Bus Timing Diagrams
t_SPF
t_SPSU
Document #: 38-07008 Rev. *B
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