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CYDM064B16_09 Datasheet, PDF (8/24 Pages) Cypress Semiconductor – 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL Dual-Port Static RAM | |||
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CYDM064B16, CYDM128B16, CYDM256B16
Table 4. Input Read Register Operation[12, 15]
SFEN CE
R/W
OE
UB
H
L
H
L
L
L
L
H
L
X
LB
ADDR IO0âIO1 IO2âIO15
Mode
L x0000-Max VALID[13] VALID[13] Standard Memory Access
L
x0000 VALID[14]
X
IRR Read
Table 5. Output Drive Register [16]
SFEN CE
H
L
L
L
L
L
R/W
H
L
H
OE
X[17]
X
L
UB
L[13]
X
X
LB
L[13]
L
L
ADDR IO0âIO4 IO5âIO15
Mode
x0000-Max VALID[13] VALID[13] Standard Memory Access
x0001 VALID[14]
X
ODR Write[16, 18]
x0001 VALID[14]
X
ODR Read[16]
Table 6. Semaphore Operation Example
Function
No action
Left port writes 0 to semaphore
Right port writes 0 to semaphore
IO0âIO15 Left
1
0
0
Left port writes 1 to semaphore
1
Left port writes 0 to semaphore
1
Right port writes 1 to semaphore
0
Left port writes 1 to semaphore
1
Right port writes 0 to semaphore
1
Right port writes 1 to semaphore
1
Left port writes 0 to semaphore
0
Left port writes 1 to semaphore
1
IO0âIO15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left Port has semaphore token
No change. Right side has no write access
to semaphore.
Right port obtains semaphore token
No change. Left port has no write access
to semaphore.
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes
12. SFEN = VIL for IRR reads
13. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
14. LB must be active (LB = VIL) for these bits to be valid.
15. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
16. SFEN = VIL for ODR reads and writes.
17. Output enable must be low (OE = VIL) during reads for valid data to be output.
18. During ODR writes data are also written to the memory.
Document #: 001-00217 Rev. *F
Page 8 of 24
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