CYDM064B16_09 Datasheet, PDF (4/24 Pages) Cypress Semiconductor – 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL Dual-Port Static RAM

CYDM064B16, CYDM128B16, CYDM256B16
Table 1. Pin Definitions - 100-Ball 0.5 mm Pitch BGA (CYDM064B16, CYDM128B16, CYDM256B16)
Left Port
Right Port
CE_L
CE_R
R/W_L
R/W_R
OE_L
A_0L–A_13L
IO_0L–IO_15L
OE_R
A_0R–A_13R
IO_0R–IO_15R
SEM_L
SEM_R
UB_L
UB_R
LB_L
LB_R
INT_L
INT_R
BUSY_L
BUSY_R
IRR0, IRR1
ODR0-ODR4
SFEN
M/S
V_CC
GND
V_DDIOL
V_DDIOR
NC
Chip Enable
Description
Read or Write Enable
Output Enable
Address (A₀–A₁₁ for 4K devices; A₀–A₁₂ for 8K devices; A₀–A₁₃ for 16K devices)
Data Bus Input or Output for x16 devices
Semaphore Enable
Upper Byte Select (IO₈–IO₁₅)
Lower Byte Select (IO₀–IO₇)
Interrupt Flag
Busy Flag
Input Read Register for CYDM064B16 and CYDM128B16
A13L and A13R for CYDM256B16.
Output Drive Register. These outputs are Open Drain.
Special Function Enable
Master or Slave Select
Core Power
Ground
Left Port IO Voltage
Right Port IO Voltage
No Connect. Leave this pin Unconnected.
Document #: 001-00217 Rev. *F
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