CY8C24894_11 Datasheet, PDF (8/46 Pages) Cypress Semiconductor – Automotive PSoC Programmable System-on-Chip Low power at high speed

CY8C24894
Pinouts
The automotive CY8C24x94 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O. However, V_SS, V_DD, and XRES are not capable of digital I/O.
56-Pin Part Pinout (with XRES pin)
Table 2. 56-Pin Part Pinout (QFN)
Pin
No.
Type
Digital Analog
Name
Description
1 I/O I, M P2[3] Direct switched capacitor block input
2 I/O I, M P2[1] Direct switched capacitor block input
3 I/O
M P4[7]
4 I/O
M P4[5]
5 I/O
M P4[3]
6 I/O
M P4[1]
7 I/O
M P3[7]
8 I/O
M P3[5]
9 I/O
M P3[3]
10 I/O
M P3[1]
11 I/O
M P5[7]
12 I/O
M P5[5]
13 I/O
M P5[3]
14 I/O
15 I/O
16 I/O
M P5[1]
M
P1[7] I²C serial clock (SCL)
M
P1[5] I²C serial data (SDA)
17 I/O
18 I/O
M P1[3]
M
P1[1] I²C SCL, ISSP SCLK^[4]
19
Power
20
DNC
V_SS Ground connection
Do not connect anything to this pin
21
DNC
Do not connect anything to this pin
22
Power
23 I/O
V_DD Supply voltage
P7[7]
24 I/O
25 I/O
P7[0]
M
P1[0] I²C SDA, ISSP SDATA^[4]
26 I/O
M P1[2]
27 I/O
M P1[4] Optional external clock (EXTCLK) input
28 I/O
M P1[6]
Figure 3. CY8C24894 56-Pin PSoC Device
AI, M, P2[3] 1
AI, M, P2[1] 2
M, P4[7] 3
M, P4[5] 4
M, P4[3] 5
M, P4[1] 6
M, P3[7] 7
M, P3[5] 8
M, P3[3] 9
M, P3[1] 10
M, P5[7] 11
M, P5[5] 12
M, P5[3] 13
M, P5[1] 14
QFN
(Top View)
42 P2[2], AI, M
41 P2[0], AI, M
40 P4[6], M
39 P4[4], M
38 P4[2], M
37 P4[0], M
36 XRES
35 P3[4], M
34 P3[2], M
33 P3[0], M
32 P5[6], M
31 P5[4], M
30 P5[2], M
29 P5[0], M
29 I/O
M P5[0]
30 I/O
31 I/O
M P5[2]
M P5[4]
Pin
Type
Name
No. _{Digital Analog}
Description
32 I/O
M P5[6]
45 I/O I, M P0[0] Analog column mux input
33 I/O
M P3[0]
46 I/O I, M P0[2] Analog column mux input
34 I/O
M P3[2]
47 I/O I, M P0[4] Analog column mux input
35 I/O
M P3[4]
48 I/O I, M P0[6] Analog column mux input
36
Input
37 I/O
M
38 I/O
M
XRES Active high external reset with internal 49
pull-down
Power
V_DD Supply voltage
P4[0]
50
Power
V_SS Ground connection
P4[2]
51 I/O I, M P0[7] Analog column mux input
39 I/O
M P4[4]
52 I/O I/O, M P0[5] Analog column mux input and column output
40 I/O
M P4[6]
53 I/O I/O, M P0[3] Analog column mux input and column output
41 I/O
I, M P2[0] Direct switched capacitor block input
54 I/O
I, M P0[1] Analog column mux input
42 I/O
I, M P2[2] Direct switched capacitor block input
55 I/O
M P2[7]
43 I/O
M P2[4] External analog ground (AGND) input 56 I/O
M P2[5]
44 I/O
M P2[6] External voltage reference (VREF) input EP
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Power
V_SS Exposed pad is not connected internally. Connect
to circuit ground for best performance
Note
4. These are the ISSP pins, which are not high Z when coming out of reset state. See the PSoC Technical Reference Manual for details.
Document Number: 001-53754 Rev. *D
Page 8 of 46
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