CY8C24894_11 Datasheet, PDF (30/46 Pages) Cypress Semiconductor – Automotive PSoC Programmable System-on-Chip Low power at high speed

CY8C24894
AC Low Power Comparator Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ T_A ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ T_A ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design
guidance only.
Table 21. AC Low Power Comparator Specifications
Symbol
Description
t_RLPC
LPC response time
Min Typ Max Units
Notes
–
–
50
μs ≥ 50 mV overdrive comparator
reference set within V_REFLPC.
AC Digital Block Specifications
Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ T_A ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ T_A ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 22. AC Digital Block Specifications
Function
Description
All
functions
Timer
Block input clock frequency
V_DD ≥ 4.75 V
V_DD < 4.75 V
Input clock frequency
No capture, V_DD ≥ 4.75 V
No capture, V_DD < 4.75 V
With capture
Capture pulse width
Counter Input clock frequency
No enable input, V_DD ≥ 4.75 V
No enable input, V_DD < 4.75 V
With enable input
Enable input pulse width
Dead
Band
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
V_DD ≥ 4.75 V
V_DD < 4.75 V
CRCPRS Input clock frequency
(PRS
Mode)
V_DD ≥ 4.75 V
V_DD < 4.75 V
CRCPRS Input clock frequency
(CRC
Mode)
SPIM
Input clock frequency
Min
–
–
–
–
–
50^[16]
–
–
–
50^[16]
20
50^[16]
50^[16]
–
–
–
–
–
–
SPIS
Trans-
mitter
Input clock (SCLK) frequency
Width of SS_Negated between transmissions
Input Clock Frequency
V_DD ≥ 4.75 V, 2 stop bits
V_DD ≥ 4.75 V, 1 stop bit
V_DD < 4.75 V
–
50^[16]
–
–
–
Typ Max Units
– 49.92^[15] MHz
– 25.92^[15] MHz
– 49.92^[15] MHz
– 25.92^[15] MHz
– 25.92^[15] MHz
–
–
ns
– 49.92^[15] MHz
– 25.92^[15] MHz
– 25.92^[15] MHz
–
–
ns
–
–
ns
–
–
ns
–
–
ns
– 49.92^[15] MHz
– 25.92^[15] MHz
– 49.92^[15] MHz
– 25.92^[15] MHz
– 25.92^[15] MHz
Notes
–
8.64^[15] MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
–
4.32^[15] MHz The input clock is the SPI SCLK in
SPIS mode.
–
–
ns
The baud rate is equal to the input
– 49.92^[15] MHz ^{clock frequency divided by 8.}
– 25.92^[15] MHz
– 25.92^[15] MHz
Notes
15. Accuracy derived from IMO with appropriate trim for V_DD range.
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-53754 Rev. *D
Page 30 of 46
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