CY8C24094_11 Datasheet, PDF (8/59 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip Low power at high speed

CY8C24094, CY8C24794
CY8C24894, CY8C24994
8. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, V_SS, V_DD, and XRES are not capable of Digital I/O.
8.1 56-Pin Part Pinout
Table 2. 56-Pin Part Pinout (QFN^[6]) See LEGEND details and footnotes in Table 3 on page 9.
Pin
Type
Name
No. Digital Analog
Description
Figure 3. CY8C24794 56-Pin PSoC Device^[3]
1 I/O I, M P2[3] Direct switched capacitor block input
2 I/O I, M P2[1] Direct switched capacitor block input
3 I/O
M P4[7]
4 I/O
M P4[5]
5 I/O
6 I/O
7 I/O
8 I/O
9 I/O
10 I/O
11 I/O
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
M P4[3]
M P4[1]
M P3[7]
M P3[5]
M P3[3]
M P3[1]
M P5[7]
M P5[5]
M P5[3]
M P5[1]
M P1[7] I²C serial clock (SCL)
M P1[5] I²C serial data (SDA)
A,I, M, P2[3] 1
A,I, M, P2[1] 2
M,P4[7] 3
M,P4[5] 4
M,P4[3] 5
M,P4[1] 6
M,P3[7] 7
M,P3[5] 8
M ,P3[3] 9
M ,P3[1] 10
M ,P5[7] 11
M ,P5[5] 12
M ,P5[3] 13
M ,P5[1] ₁₄
QFN
(Top V ie w )
42 P2[2], A, I, M
41 P2[0], A, I, M
40 P4[6],M
39 P4[4],M
38 P4[2],M
37 P4[0],M
36 P3[6],M
35 P3[4],M
34 P3[2 ],M
33 P3[0 ],M
32 P5[6 ],M
31 P5[4 ],M
30 P5[2 ],M
29 P5[0 ],M
17 I/O
18 I/O
M P1[3]
M
P1[1] I²C SCL, ISSP SCLK^[4]
19
Power
20
USB
V_SS Ground connection
D+
21
USB
D–
22
Power
23 I/O
V_DD Supply voltage
P7[7]
24 I/O
25 I/O
P7[0]
M
P1[0] I²C SDA, ISSP SDATA^[4]
26 I/O
M P1[2]
27 I/O
M P1[4] Optional external clock input (EXTCLK)
28 I/O
M P1[6]
29 I/O
30 I/O
M P5[0]
M P5[2]
Pin
Type
Name
No. Digital Analog
Description
31 I/O
M P5[4]
44 I/O
M P2[6] External voltage reference (VREF) input
32 I/O
M P5[6]
45 I/O I, M P0[0] Analog column mux input
33 I/O
M P3[0]
46 I/O I, M P0[2] Analog column mux input
34 I/O
M P3[2]
47 I/O I, M P0[4] Analog column mux input VREF
35 I/O
M P3[4]
48 I/O I, M P0[6] Analog column mux input
36 I/O
37 I/O
38 I/O
M P3[6]
M P4[0]
M P4[2]
49
Power
V_DD Supply voltage
50
Power
V_SS Ground connection
51 I/O I, M P0[7] Analog column mux input
39 I/O
M P4[4]
52 I/O I/O, M P0[5] Analog column mux input and column output
40 I/O
M P4[6]
53 I/O I/O, M P0[3] Analog column mux input and column output
41 I/O I, M P2[0] Direct switched capacitor block input 54 I/O I, M P0[1] Analog column mux input
42 I/O I, M P2[2] Direct switched capacitor block input 55 I/O
M P2[7]
43 I/O
M P2[4] External analog ground (AGND) input 56 I/O
M P2[5]
Notes
3. This part cannot be programmed with Reset mode; use Power Cycle mode when programming.
4. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
Page 8 of 59
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