CY7C1381B Datasheet, PDF (8/31 Pages) Cypress Semiconductor – 512 × 36/1M × 18 Flow-Thru SRAM

CY7C1381B
CY7C1383B
Functional Description
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
and (2) Chip Enable (CE₁, CE₂, CE₃ on TQFP, CE₁ on BGA)
is asserted active, and (3) the Write signals (GW, BWE) are all
deasserted HIGH. ADSP is ignored if CE₁ is HIGH. The
address presented to the address inputs is stored into the
address advancement logic and the Address Register while
being presented to the memory core. If the OE input is
asserted LOW, the requested data will be available at the data
outputs a maximum to t_CDV after clock rise. ADSP is ignored if
CE₁ is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) Chip Enable is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first clock cycle. If the Write inputs are
asserted active (see Write Cycle Descriptions table on page
10 for appropriate states that indicate a Write) on the next
clock rise, the appropriate data will be latched and written into
the device. The CY7C1381B/CY7C1383B provides byte Write
capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable (BWE) input with the
selected Byte Write (BW_a,b,c,d for CY7C1381B and BW_a,b for
CY7C1383B) input will selectively Write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. All I/Os are three-stated during a byte Write.
Because the CY7C1381B/CY7C1383B is a common I/O
device, the OE must be deasserted HIGH before presenting
data to the DQx inputs. Doing so will three-state the output
drivers. As a safety precaution, DQx are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE₁, CE₂, CE₃ on TQFP,
CE₁ on BGA) is asserted active, and (4) the appropriate
combination of the Write inputs (GW, BWE, and BW_x) is
asserted active to conduct a Write to the desired byte(s).
ADSC is ignored if ADSP is active LOW.
The address presented to A_[17:0] is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQx is written into the corresponding address location in
the RAM core. If a byte Write is conducted, only the selected
bytes are written. Bytes not selected during a byte Write
operation will remain unaltered. All I/Os are three-stated
during a byte Write because the CY7C1381B/CY7C1383B is
a common I/O device, the OE must be deasserted HIGH
before presenting data to the DQx inputs. Doing so will
three-state the output drivers. As a safety precaution, DQx are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1381B/CY7C1383B provides a two-bit wraparound
counter fed by A_[1:0] that implements either an interleaved or
linear burst sequence to support processors that follow a linear
burst sequence. The burst sequence is user-selectable
through MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Sequence
First
Address
A_[1:0]
00
01
10
11
Second
Address
A_[1:0]
01
00
11
10
Third
Address
A_[1:0]
10
11
00
01
Fourth
Address
A_[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A_[1:0]
00
01
10
11
Second
Address
A_[1:0]
01
10
11
00
Third
Address
A_[1:0]
10
11
00
01
Fourth
Address
A_[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. Chip Enable (CE₁, CE₂, CE₃, on TQFP, CE₁
on BGA), ADSP and ADSC must remain inactive for the
duration of t_ZZREC after the ZZ input returns LOW. Leaving ZZ
unconnected defaults the device into an active state.
Document #: 38-05196 Rev. **
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