CY7C1381B Datasheet, PDF (22/31 Pages) Cypress Semiconductor – 512 × 36/1M × 18 Flow-Thru SRAM

CY7C1381B
CY7C1383B
1
Switching Waveforms
Write Cycle Timing^{[16, 17]}
CLK
t_ADS
ADSP
ADSC
ADV
Single Write
t_CYC
t_ADH
t_ADS
t_ADH
t_ADVS
t_ADVH
Burst Write
t_CH
Pipelined Write
t_CL ADSP ignored with CE₁ inactive
ADSC initiated Write
Unselected
t_AS
ADV must be inactive for ADSP Write
ADD
WD1
WD2
t_AH
GW
BWE
t_WH
t_WS
t_WH
t_WS
t_{CES tCEH}
CE₁
CE₂
t_CES
t_CEH
CE₁ masks ADSP
WD3
Unselected with CE₂
CE₃
t_CES
OE
t_CEH
t_DH
t_DS
Data-In
High-Z
11aa
2a
2b
2c
2d
3a
= Undefined
Don’t Care
High-Z
Notes:
16. WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write Cycle Descriptions table).
17. WDx stands for Write Data to Address X.
Document #: 38-05196 Rev. **
Page 22 of 31