CY7C1372D_12 Datasheet, PDF (8/31 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture

CY7C1370D, CY7C1372D
The data written during the write operation is controlled by BW
(BW_a,b,c,d for CY7C1370D and BW_a,b for CY7C1372D) signals.
The CY7C1370D/CY7C1372D provides byte write capability that
is described in the Write Cycle Description table. Asserting the
write enable input (WE) with the selected byte write select (BW)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1370D and CY7C1372D are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQ_a,b,c,d/DQP_a,b,c,d for CY7C1370D and DQ_a,b/DQP_a,b for
CY7C1372D) inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ and DQP (DQ_a,b,c,d/DQP_a,b,c,d for
CY7C1370D and DQ_a,b/DQP_a,b for CY7C1372D) are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1370D/CY7C1372D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE₁, CE₂, and CE₃) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BW_a,b,c,d for CY7C1370D and BW_a,b for CY7C1372D) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE₁, CE₂,
and CE₃, must remain inactive for the duration of t_ZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V_DD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1:A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
01
10
11
10
11
00
11
00
01
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I_DDZZ
t_ZZS
t_ZZREC
t_ZZI
t_RZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ  V_DD 0.2 V
ZZ V_DD  0.2 V
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2t_CYC
–
0
Max
80
2t_CYC
–
2t_CYC
–
Unit
mA
ns
ns
ns
ns
Document Number: 38-05555 Rev. *N
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