CY7C1372D_12 Datasheet, PDF (22/31 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture

CY7C1370D, CY7C1372D
Switching Characteristics
Over the Operating Range
Parameter ^{[21, 22]}
Description
t_Power[23]
Clock
t_CYC
F_MAX
t_CH
t_CL
Output Times
t_CO
t_EOV
t_DOH
t_CHZ
t_CLZ
t_EOHZ
t_EOLZ
Setup Times
t_AS
t_DS
t_CENS
t_WES
t_ALS
t_CES
Hold Times
t_AH
t_DH
t_CENH
t_WEH
t_ALH
t_CEH
V_CC(typical) to the first access read or
write
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z ^{[24, 25, 26]}
Clock to low Z ^{[24, 25, 26]}
OE HIGH to output high Z ^{[24, 25, 26]}
OE LOW to output low Z ^{[24, 25, 26]}
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BW_x setup before CLK rise
ADV/LD setup before CLK rise
Chip select setup
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW_x hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
-250
Min
Max
1
–
4.0
–
–
250
1.7
–
1.7
–
–
2.6
–
2.6
1.0
–
–
2.6
1.0
–
–
2.6
0
–
1.2
–
1.2
–
1.2
–
1.2
–
1.2
–
1.2
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
-200
Min
Max
1
–
5
–
–
200
2.0
–
2.0
–
–
3.0
–
3.0
1.3
–
–
3.0
1.3
–
–
3.0
0
–
1.4
–
1.4
–
1.4
–
1.4
–
1.4
–
1.4
–
0.4
–
0.4
–
0.4
–
0.4
–
0.4
–
0.4
–
-167
Unit
Min
Max
1
–
ms
6
–
ns
–
167 MHz
2.2
–
ns
2.2
–
ns
–
3.4
ns
–
3.4
ns
1.3
–
ns
–
3.4
ns
1.3
–
ns
–
3.4
ns
0
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
1.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
0.5
–
ns
Notes
21. Timing reference is 1.5 V when V_DDQ = 3.3 V and is 1.25 V when V_DDQ = 2.5 V.
22. Test conditions shown in (a) of Figure 3 on page 21 unless otherwise noted.
23. This part has a voltage regulator internally; t_Power is the time power needs to be supplied above V_DD minimum initially, before a Read or Write operation can be initiated.
24. t_CHZ, t_CLZ, t_EOLZ, and t_EOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 21. Transition is measured ±200 mV from steady-state voltage.
25.
At any given voltage and temperature,
bus. These specifications do not imply
at^Eb^Ou^Hs^Zciosnletesnstitohnancot^En^Od^Lit^Zioann, ^dbutCt ^Hre^Zfliescltepsasrtahmanette^Cr^Ls^Zgtuoaerlaimntieneadteobvuesr
contention
worst case
between SRAMs when
user conditions. Device
sharing the
is designed
same data
to achieve
High Z prior to Low Z under the same system conditions.
26. This parameter is sampled and not 100% tested.
Document Number: 38-05555 Rev. *N
Page 22 of 31