CY7C09569V Datasheet, PDF (8/30 Pages) Cypress Semiconductor – 3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM

CY7C09569V
CY7C09579V
Switching Characteristics Over the Operating Range
-100
Parameter
Description
Min. Max.
f_MAX1
f_MAX2
t_CYC1
t_CYC2
t_CH1
t_CL1
t_CH2
t_CL2
t_R
t_F
t_SA
t_HA
t_SB
t_HB
t_SC
t_HC
t_SW
t_HW
t_SD
t_HD
t_SAD
t_HAD
t_SCN
t_HCN
t_SRST
t_HRST
t_OE
t_OLZ[8, ^9]
t_OHZ[8, ^9]
t_CD1
t_CD2
t_CA1
f_Max Flow-Through
f_Max Pipelined
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
Clock Fall Time
Address Set-Up Time
Address Hold Time
Byte Select Set-Up Time
Byte Select Hold Time
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
R/W Hold Time
Input Data Set-Up Time
Input Data Hold Time
ADS Set-Up Time
ADS Hold Time
CNTEN Set-Up Time
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Clock to Counter Address Valid -
Flow-Through
67
100
15
10
6.5
6.5
4
4
3
3
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
8
2
1
7
12.5
5
12.5
t_CA2
Clock to Counter Address Valid - Pipelined
9
t_DC
t_CKHZ[8, ^9]
t_CKLZ[8, ^9]
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
2
2
6
2
Notes:
8. This parameter is guaranteed by design, but it is not production tested.
9. Test conditions used are Load 2.
CY7C09569V
CY7C09579V
-83
Min. Max.
45
83
22
12
7.5
7.5
5
5
3
3
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
9
2
1
7
18
6
18
10
2
2
7
2
-67
Min. Max.
40
67
25
15
8.5
8.5
6.5
6.5
3
3
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
10
2
1
7
20
8
20
11
2
2
8
2
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-06054 Rev. *B
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