CY7C09569V Datasheet, PDF (1/30 Pages) Cypress Semiconductor – 3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
CY7C09569V
CY7C09579V
3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 16K x 36 organization (CY7C09569V)
— 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
— Flow-Through
— Pipelined
— Burst
• Bus-Matching Capabilities on Right Port
(x36 to x18 or x9)
• Byte-Select Capabilities on Left Port
• 100-MHz Pipelined Operation
• High-speed clock to data access 5/6/8 ns
• 3.3V Low operating power
— Active = 250 mA (typical)
— Standby = 10 μA (typical)
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Counter Address Read Back via I/O lines
• Single Chip Enable
• Automatic power-down
• Commercial and Industrial Temperature Ranges
• Compact package
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)
Logic Block Diagram
R/W_L
OE_L
B₀–B₃
CE_L
FT/Pipe_L
Left
Port
Control
Logic
I/O_0L–I/O_8L
I/O_9L–I/O_17L
I/O_18L–I/O_26L
I/O_27L–I/O_35L
A₀–A_13/14L[1]
CLK_L
ADS_L
CNTEN_L
CNTRST_L
14/15
9
9
9
9
Counter/
Address
Register
Decode
Note:
1. A₀–A₁₃ for 16K; A₀–A₁₄ for 32K devices.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
Right
Port
Control
Logic
9
9
Bus
9
Match
9
Counter/
Address
Register
Decode
R/W_R
OE_R
CE_R
FT/Pipe_R
BE
9/18/36
I/O_R
14/15
BM
SIZE
A₀–A_13/14R[1]
CLK_R
ADS_R
CNTEN_R
CNTRST_R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06054 Rev. *B
Revised April 18, 2005