CY62146EV30LL-45ZSXIT Datasheet, PDF (8/18 Pages) Cypress Semiconductor – CY62146EV30 MoBL 4-Mbit (256 K × 16) Static RAM

CY62146EV30 MoBL^®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) ^{[19, 20]}
t_RC
ADDRESS
DATA I/O
t_OHA
t_AA
PREVIOUS DATA VALID
DATA_OUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) ^{[20, 21]}
ADDRESS
CE
OE
BHE/BLE
DATA I/O
V_CC
SUPPLY
CURRENT
t_RC
t_ACE
t_DOE
t_LZOE
t_DBE
t_LZBE
HIGHIMPEDANCE
t_LZCE
t_PU
50%
t_PD
t_HZCE
t_HZOE
DATA_OUT VALID
t_HZBE
HIGH
IMPEDANCE
I_CC
50%
I_SB
Notes
19. The device is continuously selected. OE, CE = V_IL, BHE and/or BLE = V_IL.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05567 Rev. *I
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