CY62146EV30LL-45ZSXIT Datasheet, PDF (7/18 Pages) Cypress Semiconductor – CY62146EV30 MoBL 4-Mbit (256 K × 16) Static RAM

Switching Characteristics
Over the Operating Range
Parameter ^{[14, 15]}
Description
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle ^[18]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low-Z ^[16]
OE HIGH to High-Z ^{[16, 17]}
CE LOW to Low-Z ^[16]
CE HIGH to High-Z ^{[16, 17]}
CE LOW to power up
CE HIGH to power down
BLE / BHE LOW to data valid
BLE / BHE LOW to Low-Z ^[16]
BLE / BHE HIGH to High-Z ^{[16, 17]}
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE / BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High-Z ^{[16, 17]}
WE HIGH to Low-Z ^[16]
CY62146EV30 MoBL^®
45 ns
(Industrial /
Automotive-A)
Unit
Min
Max
45
–
ns
–
45
ns
10
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
0
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
45
–
ns
35
–
ns
35
–
ns
0
–
ns
0
–
ns
35
–
ns
35
–
ns
25
–
ns
0
–
ns
–
18
ns
10
–
ns
Notes
14.
Test conditions for all parameters other
pulse levels of 0 to V_CC(typ), and output
than tri-state parameters assume signal transition time
loading of the specified I_OL/I_OH as shown in the Figure
of 3 ns (1 V/ns)
3 on page 5.
or
less,
timing
reference
levels
of
V_CC(typ)/2,
input
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
16.
At any given
device.
temperature
and
voltage
condition,
t_HZCE
is
less
than
t_LZCE,
t_HZBE
is
less
than
t_LZBE,
t_HZOE
is
less
than
t_LZOE,
and
t_HZWE
is
less
than
t_LZWE
for
any
given
17. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high impedance state.
18.
The internal write
these signals can
time of the memory
terminate a write by
is defined by the overlap of
going INACTIVE. The data
iWnpEu,tCsEetu=pVa^ILn,dBhHoEldatnimd/inogr
BmLuEst=bVe_{ILre. fAelrlesnigcneadlstomthuestebdegeACofTtIhVeEstiogninailtitahtaet}
a write and
terminates
any of
the write.
Document Number: 38-05567 Rev. *I
Page 7 of 18