CY62128ELL-45ZXIT Datasheet, PDF (8/19 Pages) Cypress Semiconductor – 1-Mbit (128 K × 8) Static RAM

Switching Characteristics
Over the Operating Range
Parameter ^[16]
Description
Read Cycle
t_RC
Read cycle time
t_AA
Address to data valid
t_OHA
Data hold from address change
t_ACE
CE₁ LOW and CE₂ HIGH to data valid
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to data valid
OE LOW to Low Z^[17]
OE HIGH to High Z^{[17, 18]}
CE₁ LOW and CE₂ HIGH to Low Z^[17]
CE₁ HIGH or CE₂ LOW to High Z^{[17, 18]}
t_PU
CE₁ LOW and CE₂ HIGH to power-up
t_PD
CE₁ HIGH or CE₂ LOW to power-down
Write Cycle^[19]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_HZWE
t_LZWE
Write cycle time
CE₁ LOW and CE₂ HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to High Z^{[17, 18]}
WE HIGH to Low Z^[17]
CY62128E MoBL^®
45 ns (Industrial /
Automotive-A)
Min
Max
55 ns (Automotive-E)
Unit
Min
Max
45
–
55
–
ns
–
45
–
55
ns
10
–
10
–
ns
–
45
–
55
ns
–
22
–
25
ns
5
–
5
–
ns
–
18
–
20
ns
10
–
10
–
ns
–
18
–
20
ns
0
–
0
–
ns
–
45
–
55
ns
45
–
55
–
ns
35
–
40
–
ns
35
–
40
–
ns
0
–
0
–
ns
0
–
0
–
ns
35
–
40
–
ns
25
–
25
–
ns
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified I_OL/I_OH as shown in the Figure 4 on page 6.
17. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
18. t_HZOE, t_HZCE, and t_HZWE transitions are measured when the outputs enter a high impedance state.
19.
The internal Write time of the memory
a write by going INACTIVE. The data
is defined by the overlap of
input setup and hold timing
WmEus, _{tCbEe=reVfeILr.eAnlcl esdigntoatlshemeudsgt ebeoAf tChTeIsViEgntaol}
initiate a write and any of these
that terminates the write.
signals
can
terminate
Document Number: 38-05485 Rev. *K
Page 8 of 19