CY24272 Datasheet, PDF (8/13 Pages) Cypress Semiconductor – Rambus® XDR™ Clock Generator with Zero SDA Hold Time

CY24272
AC Operating Conditions
The AC operating conditions follow.^[6]
Parameter
Description
Condition
t_CYCLE,IN REFCLK, REFCLKB input cycle time
REFSEL = 0, /BYPASS = High
REFSEL = 1, /BYPASS = High
t_JIT,IN(cc)
t_DCIN[10]
t_RIN / t_FIN
Input Cycle to Cycle Jitter^[9]
Input Duty Cycle
Rise and Fall Times
/BYPASS = Low
Over 10,000 cycles
Measured at 20%–80% of input
voltage for REFCLK and
REFCLKB inputs
Δt_RIN / t_FIN
p_MIN[11]
f_MIN[11]
t_SR,IN
Rise and Fall Times Difference
Modulation Index for triangular modulation
Modulation Index for non-triangular modulation
Input Frequency Modulation
Input Slew Rate (measured at 20%–80% of
input voltage) for REFCLK
C_IN,REF
C_IN,CMOS
f_SCL
Capacitance at REFCLK inputs
Capacitance at CMOS inputs
SMBus clock frequency input in SCL pin
Min
9
7
4
–
40%
175
Max
11
8
–
185
60%
700
Unit
ns
ns
ns
ps
t_CYCLE
ps
–
150
ps
–
0.6
%
–
0.5^[12]
%
30
33
kHz
1
4
V/ns
–
7
pF
–
10
pF
DC 100 kHz
DC Electrical Specifications
Parameter
V_OX[6]
V_COS[6]
V_OL,ABS
V_ISET
I_DD[7]
I_DD[7]
I_OL/I_REF
I_OL,ABS
V_OL,SDA
I_OL,SDA
I_OZ
Z_OUT
Description
Differential output crossing point voltage^[13]
Output voltage swing (peak-to-peak single-ended)^[14]
Absolute output low voltage at CLK[3:0], CLK[3:0]B^[15]
Reference voltage for swing controlled current, I_REF
Power Supply Current at 2.625V, f_ref = 100 MHz, and f_out = 300 MHz
Power Supply Current at 2.625V, f_ref = 133 MHz, and f_out = 667 MHz
Ratio of output low current to reference current^[16]
Minimum current at V_OL,ABS[17]
SDA output low voltage at test condition of SDA output low current = 4 mA
SDA output low voltage at test condition of SDA voltage = 0.8V
Current during High Z per pin at CLK[3:0], CLK[3:0]B
Output dynamic impedance when clock output signal is at V_OL = 0.9V^[18]
Min
–
–
0.85
0.98
–
–
6.8
25
–
6
–
1000
Typ Max Unit
1.08
–
V
400
–
mV
–
–
V
1.0 1.02
V
–
85
mA
–
125 mA
7.0
7.2
–
–
mA
–
0.4
V
–
–
mA
–
10
μA
–
–
Ω
Notes
9. Jitter measured at crossing points and is the absolute value of the worst case deviation.
10. Measured at crossing points.
11. If input modulation is used; input modulation is allowed but not required.
12. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
13. V_OX is measured on external divider network.
14. V_COS = (clock output high voltage – clock output low voltage), measured on the external divider network.
15. V_{OL_ABS} is measured at the clock output pins of the package.
16. I_REF is equal to V_ISET/R_RC.
17. Minimum I_OL,ABS is measured at the clock output pin with R_RC = 266 ohms or less.
18. Z_OUT is defined at the output pins as (0.94V – 0.90V)/(I_0.94 – I_0.90) under conditions specified for I_{OL, ABS}.
Document Number: 001-42414 Rev. **
Page 8 of 13
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